; -------------------------------------------------------------------------------- ; @Title: STM32F4x On-Chip Peripherals ; @Props: Released ; @Author: LSD, GAJ, MHM ; @Changelog: 2016-07-26 GAJ ; 2017-05-22 MHM ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: RM0090.pdf (Rev.12 2016-05), RM0368.pdf (Rev.4 2015-05), ; RM0383.pdf (Rev.1 2014-07), RM0386.pdf (Rev.2 2015-11), ; RM0390.pdf (Rev.2 2016-01), DM00035129.pdf (Rev.7 2016-03), ; DM00037051.pdf (Rev.7 2016-03), DM00071990.pdf (Rev.8 2016-01), ; DM00077036.pdf (Rev.9 2016-01), DM00086815.pdf (Rev.5 2015-08), ; DM00102166.pdf (Rev.3 2015-01), DM00115249.pdf (Rev.4 2015-02), ; DM00141306.pdf (Rev.5 2015-11), DM00208574.pdf (Rev.3 2016-03), ; DM00219980.pdf (Rev.3 2016-03), ; stm32f410_DM00180366.pdf (Rev.2 2015-10), ; stm32f412_DM00180369.pdf (Rev.4 2016-06), ; stm32f413xx_423xx_DM00305666.pdf (Rev.2 2016-12), ; stm32f479xx_469xx_DM00208574.pdf (Rev.3 2017-01), ; ds_stm32f469xx_DM00219980.pdf (Rev.3 2016-03), ; ds_stm32f423xH_DM00214043.pdf (Rev.4 2017-01), ; ds_stm32f413xG_xH_DM00214043.pdf (Rev.3 2016-12), ; ds_stm32f412xE_xG_DM00214043.pdf (Rev.4 2016-05), ; ds_stm32f410x8_xB_DM00214043.pdf (Rev.3 2016-08) ; @Core: Cortex-M4 ; @Chip: STM32F401CD, STM32F401CE, STM32F401RD, STM32F401RE ; STM32F401VD, STM32F401VE, STM32F410C8, STM32F410CB ; STM32F410R8, STM32F410RB, STM32F410T8, STM32F410TB ; STM32F411CC, STM32F411CE, STM32F411RC, STM32F411RE ; STM32F411VC, STM32F411VE, STM32F412CE, STM32F412CG ; STM32F412RE, STM32F412RG, STM32F412VE, STM32F412VG ; STM32F412ZE, STM32F412ZG, STM32F413CG, STM32F413CH ; STM32F413MG, STM32F413MH, STM32F413RG, STM32F413RH ; STM32F413VG, STM32F413VH, STM32F413ZG, STM32F413ZH ; STM32F423CH, STM32F423MH, STM32F423RH, STM32F423VH ; STM32F423ZH, STM32F427AG, STM32F427AI, STM32F429AG ; STM32F429AI, STM32F429BE, STM32F429IE, STM32F429NE ; STM32F429VE, STM32F429ZE, STM32F437AI, STM32F439AI ; STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE ; STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE ; STM32F469AE, STM32F469AG, STM32F469AI, STM32F469BE ; STM32F469BG, STM32F469BI, STM32F469IE, STM32F469IG ; STM32F469II, STM32F469NE, STM32F469NG, STM32F469NI ; STM32F469VE, STM32F469VG, STM32F469VI, STM32F469ZE ; STM32F469ZG, STM32F469ZI, STM32F479AG, STM32F479AI ; STM32F479BG, STM32F479BI, STM32F479IG, STM32F479II ; STM32F479NG, STM32F479NI, STM32F479VG, STM32F479VI ; STM32F479ZG, STM32F479ZI ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32f4x.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems: ; 1) No base address for FMPI2C module in STM32F446xx Reference Manual ; 2) bit 6. name conflict in RCC_AHB2ENR for STM32F423xx in stm32f413xx_423xx_DM00305666.pdf ; implemented as RNGEN ; 3) bit 20. name conflict in RCC_APB1ENR in stm32f413xx_423xx_DM00305666.pdf ; implemented as UART5EN ; 4) bit 28. name conflict in RCC_DCKCFGR in stm32f479xx_469xx_DM00208574.pdf ; implemented as SDIOSEL ; 5) CKGATENR.EVTCL_CKEN description missing in stm32f412_DM00180369.pdf ; and stm32f413xx_423xx_DM00305666.pdf ; 6) DBGMCU_APB1_FZ.DBG_I2C3_SMBUS_TIMEOUT not shown on bit list but listed ; in register description in stm32f410_DM00180366.pdf. Bit implemented. ; 7) SDIO: SDIO_ICR described as write-only, bits described as r/w ; implemented as r/w. ; 8) I2S: unkown SPI_I2SCFGR.ASTREN bit access for STM32F410x ; implemented as r/w ; 9) RTC: RTC_ISR register missing from register map in stm32f413xx_423xx_DM00305666.pdf ; Register is listed in documentation. Implemented like in similar MCUs. ; 10) TIM2 to TIM5: register TIMx_BDTR mentioned in TIMx_CCMR1.OC1PE but not present on the list ; doc: stm32F410_DM00180366.pdf, stm32f412_DM00180369.pdf ; 11) ADC_CR.EXTSEL, ADC_CR.JEXTSEL states not specified in stm32f413xx_423xx_DM00305666.pdf ; 12) ds_stm32f469xx_DM00219980.pdf: on pg. 14 STM32F469I* listed as having 24 ADC channels ; pin functions on pg. 56 show STM32F469I* has 16 ADC channels. Implemented 16 channels. ; 13) ds_stm32f469xx_DM00219980.pdf: on pg. 14 STM32F469I* listed as having 16 ADC channels ; pin functions on pg. 56 show STM32F469I* has 24 ADC channels. Implemented 24 channels. ; 14) stm32f479x_DM00208574.pdf: on pg. 14 STM32F479A* listed as having 24 ADC channels ; pin functions on pg. 56 show STM32F479A* has 16 ADC channels. Implemented 16 channels. width 0xB tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end config 16. 8. tree "FMI (Flash Memory Interface)" base ad:0x40023C00 width 15. sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F411*")||cpuis("STM32F401*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423")) if (((per.l(ad:0x40023C00))&0x600)==0x600) group.long 0x00++0x3 line.long 0x00 "FLASH_ACR,Flash Access Control Register" rbitfld.long 0x00 12. " DCRST ,Data cache reset" "No reset,Reset" rbitfld.long 0x00 11. " ICRST ,Instruction cache reset" "No reset,Reset" bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,Five wait states,Six wait states,Seven wait states,Eight wait states,Nine wait states,Ten wait states,Eleven wait states,Twelve wait states,Thirteen wait states,Fourteen wait states,Fifteen wait states" elif (((per.l(ad:0x40023C00))&0x600)==0x200) group.long 0x00++0x3 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 12. " DCRST ,Data cache reset" "No reset,Reset" rbitfld.long 0x00 11. " ICRST ,Instruction cache reset" "No reset,Reset" bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,Five wait states,Six wait states,Seven wait states,Eight wait states,Nine wait states,Ten wait states,Eleven wait states,Twelve wait states,Thirteen wait states,Fourteen wait states,Fifteen wait states" elif (((per.l(ad:0x40023C00))&0x600)==0x400) group.long 0x00++0x3 line.long 0x00 "FLASH_ACR,Flash Access Control Register" rbitfld.long 0x00 12. " DCRST ,Data cache reset" "No reset,Reset" bitfld.long 0x00 11. " ICRST ,Instruction cache reset" "No reset,Reset" bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,Five wait states,Six wait states,Seven wait states,Eight wait states,Nine wait states,Ten wait states,Eleven wait states,Twelve wait states,Thirteen wait states,Fourteen wait states,Fifteen wait states" else group.long 0x00++0x3 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 12. " DCRST ,Data cache reset" "No reset,Reset" bitfld.long 0x00 11. " ICRST ,Instruction cache reset" "No reset,Reset" bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,Five wait states,Six wait states,Seven wait states,Eight wait states,Nine wait states,Ten wait states,Eleven wait states,Twelve wait states,Thirteen wait states,Fourteen wait states,Fifteen wait states" endif else group.long 0x00++0x3 line.long 0x00 "FLASH_ACR,Flash Access Control Register" bitfld.long 0x00 12. " DCRST ,Data cache reset" "No reset,Reset" bitfld.long 0x00 11. " ICRST ,Instruction cache reset" "No reset,Reset" bitfld.long 0x00 10. " DCEN ,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 9. " ICEN ,Instruction cache enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PRFTEN ,Prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,Three wait states,Four wait states,Five wait states,Six wait states,Seven wait states" endif sif (cpuis("STM32F20*")||cpuis("STM32F4*")) wgroup.long 0x04++0x07 line.long 0x00 "FLASH_KEYR,Flash Key Register" line.long 0x04 "FLASH_OPTKEYR,Flash Option Key Register" group.long 0x0C++0x0B line.long 0x00 "FLASH_SR,Flash Status Register" rbitfld.long 0x00 16. " BSY ,Busy" "Not busy,Busy" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F411*")||cpuis("STM32F401*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")) eventfld.long 0x00 8. " RDERR ,Proprietary readout protection (PCROP) error" "No error,Error" textline " " endif eventfld.long 0x00 7. " PGSERR ,Programming sequence error" "No error,Error" eventfld.long 0x00 6. " PGPERR ,Programming parallelism error" "No error,Error" eventfld.long 0x00 5. " PGAERR ,Programming alignment error" "No error,Error" textline " " eventfld.long 0x00 4. " WRPERR ,Write protection error" "No error,Error" eventfld.long 0x00 1. " OPERR ,Operation error" "No error,Error" eventfld.long 0x00 0. " EOP ,End of operation" "No,Yes" line.long 0x04 "FLASH_CR,Flash Control Register" bitfld.long 0x04 31. " LOCK ,FLASH_CR register lock" "Not locked,Locked" bitfld.long 0x04 25. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " STRT ,Triggers an erase operation" "Not erased,Erased" textline " " sif ((cpuis("STM32F42*")&&!cpuis("STM32F423*"))||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x04 15. " MER1 ,Mass erase of bank 2 sectors" "Not activated,Activated" textline " " endif bitfld.long 0x04 8.--9. " PSIZE ,Program size" "x8,x16,x32,x64" textline " " sif ((cpuis("STM32F42*")&&!cpuis("STM32F423*"))||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x04 3.--7. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " elif (cpuis("STM32F446*")||cpuis("STM32F411*")||cpuis("STM32F401*")) bitfld.long 0x04 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,,,,,user specific,user configuration,?..." textline " " elif (cpuis("STM32F410*")) bitfld.long 0x04 3.--6. " SNB ,Sector number" "0,1,2,3,4,,,,,,,,User specific,User configuration,?..." textline " " elif (cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")) bitfld.long 0x04 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,User specific,User configuration,?..." textline " " else bitfld.long 0x04 3.--6. " SNB ,Sector number" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " endif bitfld.long 0x04 2. " MER ,Erase all user sectors" "Not activated,Activated" bitfld.long 0x04 1. " SER ,Sector erase" "Not activated,Activated" textline " " bitfld.long 0x04 0. " PG ,Flash programming" "Not activated,Activated" sif (cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")||cpuis("STM32F469*")||cpuis("STM32F479*")) if (((per.l(ad:0x40023C00+0x14))&0x80000000)==0x80000000) group.long 0x14++0x3 line.long 0x00 "FLASH_OPTCR,Flash Option Control Register" bitfld.long 0x00 31. " SPRMOD ,Selection of protection mode for nWPRi bits" "Write protection,PCROP protection" sif (cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 30. " DB1M ,Dual-bank on 1 Mbyte Flash memory devices" "Single,Dual" endif textline " " sif cpuis("STM32F410*") bitfld.long 0x00 20. " NWRP[4] ,Sector 4 PCROP protection" "Not active,Active" bitfld.long 0x00 19. " [3] ,Sector 3 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 18. " [2] ,Sector 2 PCROP protection" "Not active,Active" bitfld.long 0x00 17. " [1] ,Sector 1 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 16. " [0] ,Sector 0 PCROP protection" "Not active,Active" elif (cpuis("STM32F412*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 27. " NWRP[11] ,Sector 11 PCROP protection" "Not active,Active" bitfld.long 0x00 26. " [10] ,Sector 10 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 25. " [9] ,Sector 9 PCROP protection" "Not active,Active" bitfld.long 0x00 24. " [8] ,Sector 8 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 23. " [7] ,Sector 7 PCROP protection" "Not active,Active" bitfld.long 0x00 22. " [6] ,Sector 6 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 21. " [5] ,Sector 5 PCROP protection" "Not active,Active" bitfld.long 0x00 20. " [4] ,Sector 4 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 19. " [3] ,Sector 3 PCROP protection" "Not active,Active" bitfld.long 0x00 18. " [2] ,Sector 2 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 17. " [1] ,Sector 1 PCROP protection" "Not active,Active" bitfld.long 0x00 16. " [0] ,Sector 0 PCROP protection" "Not active,Active" elif (cpuis("STM32F413*")||cpuis("STM32F423*")) bitfld.long 0x00 30. " NWRP14_15 ,Sectors 14 and 15 PCROP protection" "Not active,Active" bitfld.long 0x00 29. " [13] ,Sector 13 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 28. " [12] ,Sector 12 PCROP protection" "Not active,Active" bitfld.long 0x00 27. " [11] ,Sector 11 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 26. " [10] ,Sector 10 PCROP protection" "Not active,Active" bitfld.long 0x00 25. " [9] ,Sector 9 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 24. " [8] ,Sector 8 PCROP protection" "Not active,Active" bitfld.long 0x00 23. " [7] ,Sector 7 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 22. " [6] ,Sector 6 PCROP protection" "Not active,Active" bitfld.long 0x00 21. " [5] ,Sector 5 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 20. " [4] ,Sector 4 PCROP protection" "Not active,Active" bitfld.long 0x00 19. " [3] ,Sector 3 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 18. " [2] ,Sector 2 PCROP protection" "Not active,Active" bitfld.long 0x00 17. " [1] ,Sector 1 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 16. " [0] ,Sector 0 PCROP protection" "Not active,Active" endif textline " " hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protection" textline " " bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Generated,Not generated" bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Generated,Not generated" textline " " bitfld.long 0x00 5. " WDG_SW ,Independent watchdog type" "Hardware,Software" sif (cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 4. " BFB2 ,Dual bank boot option" "Disabled,Enabled" endif textline " " bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset Level" "VBOR3,VBOR2,VBOR1,POR/PDR" bitfld.long 0x00 1. " OPTSTRT ,Option start" "No effect,Started" bitfld.long 0x00 0. " OPTLOCK ,FLASH_OPTCR register" "Not locked,Locked" else group.long 0x14++0x3 line.long 0x00 "FLASH_OPTCR,Flash Option Control Register" bitfld.long 0x00 31. " SPRMOD ,Selection of protection mode for nWPRi bits" "Write protection,PCROP protection" sif (cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 30. " DB1M ,Dual-bank on 1 Mbyte Flash memory devices" "Single,Dual" endif textline " " sif cpuis("STM32F410*") bitfld.long 0x00 20. " NWRP[4] ,Sector 4 write protection" "Active,Not active" bitfld.long 0x00 19. " [3] ,Sector 3 write protection" "Active,Not active" textline " " bitfld.long 0x00 18. " [2] ,Sector 2 write protection" "Active,Not active" bitfld.long 0x00 17. " [1] ,Sector 1 write protection" "Active,Not active" textline " " bitfld.long 0x00 16. " [0] ,Sector 0 write protection" "Active,Not active" elif (cpuis("STM32F412*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 27. " NWRP[11] ,Sector 11 write protection" "Active,Not active" bitfld.long 0x00 26. " [10] ,Sector 10 write protection" "Active,Not active" textline " " bitfld.long 0x00 25. " [9] ,Sector 9 write protection" "Active,Not active" bitfld.long 0x00 24. " [8] ,Sector 8 write protection" "Active,Not active" textline " " bitfld.long 0x00 23. " [7] ,Sector 7 write protection" "Active,Not active" bitfld.long 0x00 22. " [6] ,Sector 6 write protection" "Active,Not active" textline " " bitfld.long 0x00 21. " [5] ,Sector 5 write protection" "Active,Not active" bitfld.long 0x00 20. " [4] ,Sector 4 write protection" "Active,Not active" textline " " bitfld.long 0x00 19. " [3] ,Sector 3 write protection" "Active,Not active" bitfld.long 0x00 18. " [2] ,Sector 2 write protection" "Active,Not active" textline " " bitfld.long 0x00 17. " [1] ,Sector 1 write protection" "Active,Not active" bitfld.long 0x00 16. " [0] ,Sector 0 write protection" "Active,Not active" elif (cpuis("STM32F413*")||cpuis("STM32F423*")) bitfld.long 0x00 30. " NWRP14_15 ,Sectors 14 and 15 write protection" "Active,Not active" bitfld.long 0x00 29. " [13] ,Sector 13 write protection" "Active,Not active" textline " " bitfld.long 0x00 28. " [12] ,Sector 12 write protection" "Active,Not active" bitfld.long 0x00 27. " [11] ,Sector 11 write protection" "Active,Not active" textline " " bitfld.long 0x00 26. " [10] ,Sector 10 write protection" "Active,Not active" bitfld.long 0x00 25. " [9] ,Sector 9 write protection" "Active,Not active" textline " " bitfld.long 0x00 24. " [8] ,Sector 8 write protection" "Active,Not active" bitfld.long 0x00 23. " [7] ,Sector 7 write protection" "Active,Not active" textline " " bitfld.long 0x00 22. " [6] ,Sector 6 write protection" "Active,Not active" bitfld.long 0x00 21. " [5] ,Sector 5 write protection" "Active,Not active" textline " " bitfld.long 0x00 20. " [4] ,Sector 4 write protection" "Active,Not active" bitfld.long 0x00 19. " [3] ,Sector 3 write protection" "Active,Not active" textline " " bitfld.long 0x00 18. " [2] ,Sector 2 write protection" "Active,Not active" bitfld.long 0x00 17. " [1] ,Sector 1 write protection" "Active,Not active" textline " " bitfld.long 0x00 16. " [0] ,Sector 0 write protection" "Active,Not active" endif textline " " hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protection" textline " " bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the standby mode" "Generated,Not generated" bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the stop mode" "Generated,Not generated" textline " " bitfld.long 0x00 5. " WDG_SW ,Independent watchdog type" "Hardware,Software" sif (cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 4. " BFB2 ,Dual bank boot option" "Disabled,Enabled" endif textline " " bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset Level" "VBOR3,VBOR2,VBOR1,POR/PDR" bitfld.long 0x00 1. " OPTSTRT ,Option start" "No effect,Started" bitfld.long 0x00 0. " OPTLOCK ,FLASH_OPTCR register lock" "Not locked,Locked" endif else group.long 0x14++0x03 line.long 0x00 "FLASH_OPTCR,Flash Option Control register" sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 31. " SPRMOD ,Selection of protection mode for nWPRi bits" "Write protection,PCROP protection" bitfld.long 0x00 30. " DB1M ,Dual-bank on 1 Mbyte Flash memory devices" "Single,Dual" textline " " elif (cpuis("STM32F446*")||cpuis("STM32F411*")||cpuis("STM32F401*")) bitfld.long 0x00 31. " SPRMOD ,Selection of protection mode for nWPRi bits" "Write protection,PCROP protection" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F411*")||cpuis("STM32F401*")) hexmask.long.byte 0x00 16.--23. 1. " NWRP ,Not write protect" hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protection" else hexmask.long.word 0x00 16.--27. 1. " NWRP ,Not write protect" hexmask.long.byte 0x00 8.--15. 1. " RDP ,Read protection" endif textline " " bitfld.long 0x00 7. " NRST_STDBY ,Reset generated when entering the Standby mode" "No reset,Reset" bitfld.long 0x00 6. " NRST_STOP ,Reset generated when entering the Stop mode" "No reset,Reset" textline " " bitfld.long 0x00 5. " WDG_SW ,Watchdog" "Hardware,Software" textline " " sif (cpuis("STM32F437AI")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 4. " BFB2 ,Dual-bank Boot option byte" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2.--3. " BOR_LEV ,BOR reset Level" "VBOR3,VBOR2,VBOR1,VBOR0" bitfld.long 0x00 1. " OPTSTRT ,Option start" "No effect,Started" bitfld.long 0x00 0. " OPTLOCK ,FLASH_OPTCR register" "Not locked,Locked" endif sif ((cpuis("STM32F42*")&&!cpuis("STM32F423*"))||cpuis("STM32F43*")) group.long 0x18++0x03 line.long 0x00 "FLASH_OPTCR1,Flash Option Control Register 1" hexmask.long.word 0x00 16.--27. 1. " NWRP ,Not write protect" elif (cpuis("STM32F469*")||cpuis("STM32F479*")) if (((per.l(ad:0x40023C00+0x14))&0x80000000)==0x80000000) group.long 0x18++0x03 line.long 0x00 "FLASH_OPTCR1,Flash Option Control Register 1" bitfld.long 0x00 27. " NWRP[11] ,Sector 23 PCROP protection" "Not active,Active" bitfld.long 0x00 26. " [10] ,Sector 22 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 25. " [9] ,Sector 21 PCROP protection" "Not active,Active" bitfld.long 0x00 24. " [8] ,Sector 20 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 23. " [7] ,Sector 19 PCROP protection" "Not active,Active" bitfld.long 0x00 22. " [6] ,Sector 18 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 21. " [5] ,Sector 17 PCROP protection" "Not active,Active" bitfld.long 0x00 20. " [4] ,Sector 16 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 19. " [3] ,Sector 15 PCROP protection" "Not active,Active" bitfld.long 0x00 18. " [2] ,Sector 14 PCROP protection" "Not active,Active" textline " " bitfld.long 0x00 17. " [1] ,Sector 13 PCROP protection" "Not active,Active" bitfld.long 0x00 16. " [0] ,Sector 12 PCROP protection" "Not active,Active" else group.long 0x18++0x03 line.long 0x00 "FLASH_OPTCR1,Flash Option Control Register 1" bitfld.long 0x00 27. " NWRP[11] ,Sector 23 write protection" "Active,Not active" bitfld.long 0x00 26. " [10] ,Sector 22 write protection" "Active,Not active" textline " " bitfld.long 0x00 25. " [9] ,Sector 21 write protection" "Active,Not active" bitfld.long 0x00 24. " [8] ,Sector 20 write protection" "Active,Not active" textline " " bitfld.long 0x00 23. " [7] ,Sector 19 write protection" "Active,Not active" bitfld.long 0x00 22. " [6] ,Sector 18 write protection" "Active,Not active" textline " " bitfld.long 0x00 21. " [5] ,Sector 17 write protection" "Active,Not active" bitfld.long 0x00 20. " [4] ,Sector 16 write protection" "Active,Not active" textline " " bitfld.long 0x00 19. " [3] ,Sector 15 write protection" "Active,Not active" bitfld.long 0x00 18. " [2] ,Sector 14 write protection" "Active,Not active" textline " " bitfld.long 0x00 17. " [1] ,Sector 13 write protection" "Active,Not active" bitfld.long 0x00 16. " [0] ,Sector 12 write protection" "Active,Not active" endif endif endif width 0x0B tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40023000 width 9. group.long 0x00++0x07 line.long 0x00 "CRC_DR, Data register" line.long 0x04 "CRC_IDR, Independent data register" hexmask.long.byte 0x04 0.--7. 1. " IDR ,General-purpose 8-bit data register bits" wgroup.long 0x08++0x03 line.long 0x00 "CRC_CR, Control register" bitfld.long 0x00 0. " RESET , Reset CRC bit" "No reset,Reset" width 0x0B tree.end tree "PWR_CR (Power Control Register)" base ad:0x40007000 width 9. group.long 0x00++0x3 line.long 0x00 "PWR_CR,Power Control Register" sif (cpuis("STM32F411*")||cpuis("STM32F401*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")) sif (!cpuis("STM32F401*")) bitfld.long 0x00 21. " FISSR ,Flash interface stop while system run" "Not stopped,Stopped" bitfld.long 0x00 20. " FMSSR ,Flash memory sleep system run" "Standard mode,STOP/DeepPower Down mode" textline " " endif bitfld.long 0x00 14.--15. " VOS ,Regulator voltage scaling output selection" ",Scale 3,Scale 2,Scale 1" textline " " bitfld.long 0x00 13. " ADCDC1 ,ADC accuracy option 1" "No effect,Activated" bitfld.long 0x00 11. " MRLVDS ,Main regulator low voltage in deep sleep mode" "Disabled,Enabled" bitfld.long 0x00 10. " LPLVDS ,Low-power regulator low voltage in deep sleep mode" "Disabled,Enabled" textline " " elif (cpuis("STM32F446*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) sif (cpuis("STM32F446*")) bitfld.long 0x00 21. " FISSR ,Flash interface stop while system run" "Not stopped,Stopped" bitfld.long 0x00 20. " FMSSR ,Flash memory sleep system run" "Standard mode,STOP/DeepPower Down mode" textline " " endif bitfld.long 0x00 18.--19. " UDEN ,Under-drive enable in stop mode" "Disabled,,,Enabled" bitfld.long 0x00 17. " ODSWEN ,Over-drive switching enabled" "Disabled,Enabled" bitfld.long 0x00 16. " ODEN ,Over-drive enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " VOS ,Regulator voltage scaling output selection" ",Scale 3,Scale 2,Scale 1" textline " " bitfld.long 0x00 13. " ADCDC1 ,ADC accuracy option 1" "No effect,Activated" bitfld.long 0x00 11. " MRUDS ,Main regulator in deepsleep under-drive mode" "Disabled,Enabled" bitfld.long 0x00 10. " LPUDS ,Low-power regulator in deepsleep under-drive mode" "Disabled,Enabled" textline " " elif (cpuis("STM32F40*")||cpuis("STM32F41*")) bitfld.long 0x00 14. " VOS ,Regulator voltage scaling output selection" "Scale 2,Scale 1" textline " " endif bitfld.long 0x00 9. " FPDS ,Flash power down in stop mode" "No power down,Power down" bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes" sif (cpuis("STM32F411*")||cpuis("STM32F401*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")) textline " " bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V" else textline " " bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "2.0V,2.1V,2.3V,2.5V,2.6V,2.7V,2.8V,2.9V" endif textline " " bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled" sif cpuis("STM32F4*") textline " " bitfld.long 0x00 3. " CSBF ,Clear STANDBY flag" "No effect,Clear" bitfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Clear" eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Clear" endif textline " " bitfld.long 0x00 1. " PDDS ,Power down deepsleep" "Stop,Standby" bitfld.long 0x00 0. " LPDS ,Low-power deepsleep in stop mode" "Off,On" if (((per.l(ad:0x40007000))&0x10)==0x10) group.long 0x04++0x3 line.long 0x00 "PWR_CSR,Power Control/Status Register" sif (cpuis("STM32F446*")||(cpuis("STM32F42*")&&!cpuis("STM32F423*"))||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 18.--19. " UDRDY ,Under-drive ready flag" "Disabled,,,Activated" rbitfld.long 0x00 17. " ODSWRDY ,Over-drive mode switching ready" "Not ready,Ready" rbitfld.long 0x00 16. " ODRDY ,Over-drive mode ready" "Not ready,Ready" textline " " endif sif (cpuis("STM32F4*")) rbitfld.long 0x00 14. " VOSRDY ,Regulator voltage scaling output selection ready bit" "Not ready,Ready" textline " " endif bitfld.long 0x00 9. " BRE ,Backup regulator enable" "Disabled,Enabled" sif (cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")) bitfld.long 0x00 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled" bitfld.long 0x00 6. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled" textline " " else bitfld.long 0x00 8. " EWUP ,Enable WKUP pin" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 3. " BRR ,Backup regulator ready" "Not ready,Ready" rbitfld.long 0x00 2. " PVDO ,PVD output" "VDD/VDDA>PVD threshold,VDD/VDDA=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x00)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" rbitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0xA0001000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0xA0001000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif textline " " if (((per.l(ad:0xA0001000+0x08))&0x20)==0x00) if (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000) group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" else group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" endif else if (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000) rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" else rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" endif endif if (((per.l(ad:0xA0001000+0x14))&0xC000000)==(0x0||0x4000000)) rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--13. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,Full,?..." textline " " else bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..." textline " " endif bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 2. " FTF ,FIFO threshold flag" "Not reached,Reached" textline " " bitfld.long 0x00 1. " TCF ,Transfer complete flag" "Not transferred,Transferred" bitfld.long 0x00 0. " TEF ,Transfer error flag" "No error,Error" elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000) rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--13. " FLEVEL ,FIFO level" "Empty,?..." textline " " else bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,?..." textline " " endif bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 1. " TCF ,Transfer has been aborted" "Not aborted,Aborted" elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==0x8000000) hgroup.long 0x08++0x03 hide.long 0x00 "QUADSPI_SR,QUADSPI Status Register" in endif if (((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000) wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" elif (((per.l(ad:0xA0001000+0x14))&0xC000000)==(0x0||0x4000000)) wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" bitfld.long 0x00 0. " CTEF ,Clear transfer error flag" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 3. " CSMF ,Clear status match flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" endif if (((per.l(ad:0xA0001000+0x08))&0x20)==0x0) group.long 0x10++0x07 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" line.long 0x04 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")) bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk" textline " " elif cpuis("STM32F412*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 30. " DHHC ,DDR hold" "Analog delay,1/4 QUADSPI clk" textline " " endif bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" textline " " bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" else rgroup.long 0x10++0x07 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" line.long 0x04 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")) bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk" textline " " elif cpuis("STM32F412*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 30. " DHHC ,DDR hold" "Analog delay,1/4 QUADSPI clk" textline " " endif bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" textline " " bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" endif if (((per.l(ad:0xA0001000+0x08))&0x20)==0x0||((per.l(ad:0xA0001000+0x14))&0xC000000)==0xC000000) rgroup.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" else group.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" endif if (((per.l(ad:0xA0001000+0x08))&0x20)==0x0) group.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Registers" else rgroup.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Registers" endif if (((per.l(ad:0xA0001000+0x14))&0xC000000)==(0x8000000||0x00||0x4000000)) hgroup.long 0x20++0x03 hide.long 0x00 "QUADSPI_DR,QUADSPI Data Register" in else group.long 0x20++0x03 line.long 0x00 "QUADSPI_DR,QUADSPI Data Register" endif if (((per.l(ad:0xA0001000+0x08))&0x20)==0x0) group.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI Low-power Timeout Register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" else rgroup.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI low-power timeout register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" endif width 0x0B tree.end elif (cpuis("STM32F412*")&&!cpuis("STM32F412C*"))||(cpuis("STM32F413*")&&!cpuis("STM32F413C*"))||(cpuis("STM32F423?H")&&!(cpu()=="STM32F423CH")) tree "QUADSPI (QuadSPI)" base ad:0x90000000 width 15. if ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x00)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x00)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x4000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--12. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16,free>=17,free>=18,free>=19,free>=20,free>=21,free>=22,free>=23,free>=24,free>=25,free>=26,free>=27,free>=28,free>=29,free>=30,free>=31,free>=32" textline " " else bitfld.long 0x00 8.--11. " FTHRES ,FIFO threshold level" "free>=1,free>=2,free>=3,free>=4,free>=5,free>=6,free>=7,free>=8,free>=9,free>=10,free>=11,free>=12,free>=13,free>=14,free>=15,free>=16" textline " " endif sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" rbitfld.long 0x00 3. " TCEN ,Timeout counter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x00)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" bitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" bitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" bitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" elif ((((per.l(ad:0x90000000+0x14))&0xC000000)==0x8000000)&&(((per.l(ad:0x90000000+0x08))&0x20)==0x20)) group.long 0x00++0x03 line.long 0x00 "QUADSPI_CR,QUADSPI Control Register" hexmask.long.byte 0x00 24.--31. 1. " PRESCALER ,Clock prescaler" rbitfld.long 0x00 23. " PMM ,Polling match mode" "AND mode,OR mode" rbitfld.long 0x00 22. " APMS ,Automatic poll mode stop" "Running,Stopped" bitfld.long 0x00 20. " TOIE ,TimeOut interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SMIE ,Status match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " FTIE ,FIFO threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) rbitfld.long 0x00 7. " FSEL ,Flash memory selection" "FLASH 1,FLASH 2" rbitfld.long 0x00 6. " DFM ,Dual-flash mode enable" "Disabled,Enabled" textline " " endif rbitfld.long 0x00 4. " SSHIFT ,Sample shift" "No shift,1/2 cycle shift" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 1. " ABORT ,Abort request" "Not requested,Requested" bitfld.long 0x00 0. " EN ,Enable the QUADSPI" "Disabled,Enabled" endif textline " " if (((per.l(ad:0x90000000+0x08))&0x20)==0x00) if (((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000) group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" else group.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" endif else if (((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000) rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,?..." bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" else rgroup.long 0x04++0x03 line.long 0x00 "QUADSPI_DCR,QUADSPI Device Configuration Register" bitfld.long 0x00 16.--20. " FSIZE ,FLASH memory size" "2B,4B,8B,16B,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 8.--10. " CSHT ,Chip select high time" ">=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8" bitfld.long 0x00 0. " CKMODE ,Mode 0 / mode 3" "Mode0,Mode3" endif endif if (((per.l(ad:0x90000000+0x14))&0xC000000)==(0x0||0x4000000)) rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--13. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,Full,?..." textline " " else bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..." textline " " endif bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 2. " FTF ,FIFO threshold flag" "Not reached,Reached" textline " " bitfld.long 0x00 1. " TCF ,Transfer complete flag" "Not transferred,Transferred" bitfld.long 0x00 0. " TEF ,Transfer error flag" "No error,Error" elif (((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000) rgroup.long 0x08++0x03 line.long 0x00 "QUADSPI_SR,QUADSPI Status Register" sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) bitfld.long 0x00 8.--13. " FLEVEL ,FIFO level" "Empty,?..." textline " " else bitfld.long 0x00 8.--12. " FLEVEL ,FIFO level" "Empty,?..." textline " " endif bitfld.long 0x00 5. " BUSY ,This bit is set when an operation is on going" "Idle,Busy" bitfld.long 0x00 4. " TOF ,Timeout flag" "No timeout,Timeout" bitfld.long 0x00 1. " TCF ,Transfer has been aborted" "Not aborted,Aborted" elif (((per.l(ad:0x90000000+0x14))&0xC000000)==0x8000000) hgroup.long 0x08++0x03 hide.long 0x00 "QUADSPI_SR,QUADSPI Status Register" in endif if (((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000) wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" elif (((per.l(ad:0x90000000+0x14))&0xC000000)==(0x0||0x4000000)) wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" bitfld.long 0x00 0. " CTEF ,Clear transfer error flag" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "QUADSPI_FCR,QUADSPI Flag Clear Register" bitfld.long 0x00 4. " CTOF ,Clear timeout flag" "No effect,Clear" bitfld.long 0x00 3. " CSMF ,Clear status match flag" "No effect,Clear" bitfld.long 0x00 1. " CTCF ,Clear transfer complete flag" "No effect,Clear" endif if (((per.l(ad:0x90000000+0x08))&0x20)==0x0) group.long 0x10++0x07 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" line.long 0x04 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")) bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk" textline " " elif cpuis("STM32F412*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 30. " DHHC ,DDR hold" "Analog delay,1/4 QUADSPI clk" textline " " endif bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" textline " " bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" else rgroup.long 0x10++0x07 line.long 0x00 "QUADSPI_DLR,QUADSPI Data Length Register" line.long 0x04 "QUADSPI_CCR,QUADSPI Communication Configuration Register" bitfld.long 0x04 31. " DDRM ,Double data rate mode" "Disabled,Enabled" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F7*")) bitfld.long 0x04 30. " DHHC ,DDR hold half cycle" "Analog delay,1/2 system clk" textline " " elif cpuis("STM32F412*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 30. " DHHC ,DDR hold" "Analog delay,1/4 QUADSPI clk" textline " " endif bitfld.long 0x04 28. " SIOO ,Send instruction only once mode" "Every transaction,Only first command" bitfld.long 0x04 26.--27. " FMODE ,Functional mode" "Indirect write,Indirect read,Automatic polling,Memory-mapped" bitfld.long 0x04 24.--25. " DMODE ,Data mode" "No data,Single line,Two lines,Four lines" bitfld.long 0x04 18.--22. " DCYC ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 16.--17. " ABSIZE ,Alternate bytes size" "8b,16b,24b,32b" bitfld.long 0x04 14.--15. " ABMODE ,Alternate bytes mode" "No bytes,Single line,Two lines,Four lines" bitfld.long 0x04 12.--13. " ADSIZE ,Address size" "8b,16b,24b,32b" bitfld.long 0x04 10.--11. " ADMODE ,Address mode" "No address,Single line,Two lines,Four lines" textline " " bitfld.long 0x04 8.--9. " IMODE ,Instruction mode" "No instruction,Single line,Two lines,Four lines" hexmask.long.byte 0x04 0.--7. 1. " INSTRUCTION ,Instruction to be send to the external SPI device" endif if (((per.l(ad:0x90000000+0x08))&0x20)==0x0||((per.l(ad:0x90000000+0x14))&0xC000000)==0xC000000) rgroup.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" else group.long 0x18++0x03 line.long 0x00 "QUADSPI_AR,QUADSPI Address Register" endif if (((per.l(ad:0x90000000+0x08))&0x20)==0x0) group.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Registers" else rgroup.long 0x1C++0x03 line.long 0x00 "QUADSPI_ABR,QUADSPI Alternate Bytes Registers" endif if (((per.l(ad:0x90000000+0x14))&0xC000000)==(0x8000000||0x00||0x4000000)) hgroup.long 0x20++0x03 hide.long 0x00 "QUADSPI_DR,QUADSPI Data Register" in else group.long 0x20++0x03 line.long 0x00 "QUADSPI_DR,QUADSPI Data Register" endif if (((per.l(ad:0x90000000+0x08))&0x20)==0x0) group.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI Low-power Timeout Register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" else rgroup.long 0x24++0x0F line.long 0x00 "QUADSPI_PSMKR,QUADSPI Polling Status Mask Register" bitfld.long 0x00 31. " MASK[31] ,Status mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Status mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Status mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Status mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Status mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Status mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Status mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Status mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Status mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Status mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Status mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Status mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Status mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Status mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Status mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Status mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Status mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Status mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Status mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Status mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Status mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Status mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Status mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Status mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Status mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Status mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Status mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Status mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Status mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Status mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Status mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Status mask bit 0" "Masked,Not masked" line.long 0x04 "QUADSPI_PSMAR,QUADSPI Polling Status Match Register" line.long 0x08 "QUADSPI_PIR,QUADSPI Polling Interval Register" hexmask.long.word 0x08 0.--15. 1. " INTERVAL ,Polling interval" line.long 0x0C "QUADSPI_LPTR,QUADSPI low-power timeout register" hexmask.long.word 0x0C 0.--15. 1. " TIMEOUT ,Timeout period" endif width 0x0B tree.end endif tree.open "ADC (Analog/Digital Converter)" tree "Common Registers" base ad:0x40012300 width 11. sif (cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401?D")||cpuis("STM32F401?E")) group.long 0x04++0x3 line.long 0x00 "ADC_CCR,ADC Common Control Register" bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 22. " VBATE ,VBAT enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "PCLK2/2,PCLK2/4,PCLK2/6,PCLK2/8" elif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") rgroup.long 0x00++0x03 line.long 0x00 "ADC_CSR,ADC Common Status Register" bitfld.long 0x00 5. " OVR1 ,Overrun flag of ADC1" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT1 ,Regular channel start flag of ADC1" "Not started,Started" bitfld.long 0x00 3. " JSTRT1 ,Injected channel start flag of ADC1" "Not started,Started" bitfld.long 0x00 2. " JEOC1 ,Injected channel end of conversion of ADC1" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC1 ,End of conversion of ADC1" "Not completed,Completed" bitfld.long 0x00 0. " AWD1 ,Analog watchdog flag of ADC1" "Not occurred,Occurred" group.long 0x04++0x03 line.long 0x00 "ADC_CCR,ADC Common Control Register" bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 22. " VBATE ,VBAT enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "PCLK2/2,PCLK2/4,PCLK2/6,PCLK2/8" else rgroup.long 0x00++0x3 line.long 0x00 "ADC_CSR,ADC Common Status Register" sif (!cpuis("STM32F446M?")&&!cpuis("STM32F446R?")&&!cpuis("STM32F446V?")) bitfld.long 0x00 21. " OVR3 ,Overrun flag of ADC3" "Not occurred,Occurred" bitfld.long 0x00 20. " STRT3 ,Regular channel start flag of ADC3" "Not started,Started" bitfld.long 0x00 19. " JSTRT3 ,Injected channel start flag of ADC3" "Not started,Started" bitfld.long 0x00 18. " JEOC3 ,Injected channel end of conversion of ADC3" "Not completed,Completed" textline " " bitfld.long 0x00 17. " EOC3 ,End of conversion of ADC3" "Not completed,Completed" bitfld.long 0x00 16. " AWD3 ,Analog watchdog flag of ADC3" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 13. " OVR2 ,Overrun flag of ADC2" "Not occurred,Occurred" bitfld.long 0x00 12. " STRT2 ,Regular channel start flag of ADC2" "Not started,Started" bitfld.long 0x00 11. " JSTRT2 ,Injected channel start flag of ADC2" "Not started,Started" bitfld.long 0x00 10. " JEOC2 ,Injected channel end of conversion of ADC2" "Not completed,Completed" textline " " bitfld.long 0x00 9. " EOC2 ,End of conversion of ADC2" "Not completed,Completed" bitfld.long 0x00 8. " AWD2 ,Analog watchdog flag of ADC2" "Not occurred,Occurred" bitfld.long 0x00 5. " OVR1 ,Overrun flag of ADC1" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT1 ,Regular channel start flag of ADC1" "Not started,Started" textline " " bitfld.long 0x00 3. " JSTRT1 ,Injected channel start flag of ADC1" "Not started,Started" bitfld.long 0x00 2. " JEOC1 ,Injected channel end of conversion of ADC1" "Not completed,Completed" bitfld.long 0x00 1. " EOC1 ,End of conversion of ADC1" "Not completed,Completed" bitfld.long 0x00 0. " AWD1 ,Analog watchdog flag of ADC1" "Not occurred,Occurred" group.long 0x04++0x3 line.long 0x00 "ADC_CCR,ADC Common Control Register" bitfld.long 0x00 23. " TSVREFE ,Temperature sensor and VREFINT enable" "Disabled,Enabled" bitfld.long 0x00 22. " VBATE ,VBAT enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " ADCPRE ,ADC prescaler" "PCLK2/2,PCLK2/4,PCLK2/6,PCLK2/8" textline " " bitfld.long 0x00 14.--15. " DMA ,Direct memory access mode for multi ADC mode" "Disabled,Mode 1,Mode 2,Mode 3" bitfld.long 0x00 13. " DDS ,DMA disable selection (for multi-ADC mode)" "Last transfer finished,Convertion finished" bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases" "5 * TADCCLK,6 * TADCCLK,7 * TADCCLK,8 * TADCCLK,9 * TADCCLK,10 * TADCCLK,11 * TADCCLK,12 * TADCCLK,13 * TADCCLK,14 * TADCCLK,15 * TADCCLK,16 * TADCCLK,17 * TADCCLK,18 * TADCCLK,19 * TADCCLK,20 * TADCCLK" bitfld.long 0x00 0.--4. " MULTI ,Multi ADC mode selection" "Independent mode,Dual mode/combined regular simultaneous + injected simultaneous mode,Dual mode/combined regular simultaneous + alternate trigger mode,,,Dual mode/injected simultaneous mode only,Dual mode/regular simultaneous mode only,Dual mode/interleaved mode only,,Dual mode/alternate trigger mode only,,,,,,,,Triple mode/combined regular simultaneous + injected simultaneous mode,Triple mode/combined regular simultaneous + alternate trigger mode,,,Triple mode/injected simultaneous mode only,Triple mode/regular simultaneous mode only,Triple mode/interleaved mode only,,Triple mode/alternate trigger mode only,?..." rgroup.long 0x08++0x3 line.long 0x00 "ADC_CDR,ADC Common Regular Data Register For Dual And Triple Modes" hexmask.long.word 0x00 16.--31. 1. " DATA2 ,2nd data item of a pair of regular conversions" hexmask.long.word 0x00 0.--15. 1. " DATA1 ,1st data item of a pair of regular conversions" endif width 0x0B tree.end sif cpuis("STM32F469*")||cpuis("STM32F479*") tree "ADC 1" base ad:0x40012000 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" group.long 0x00++0x03 line.long 0x00 "ADC_CR1,ADC Control Register 1" bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x00 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x00 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" textline " " sif cpuis("STM32F469A*")||cpuis("STM32F479A*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,,,,,,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F469V*")||cpuis("STM32F479V*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,,,,ADC_IN17,ADC_IN18,?..." else bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,,ADC_IN17,ADC_IN18,?..." endif if (((per.l(ad:0x40012000+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "3,15,28,56,84,112,144,480" textline " " sif !cpuis("STM32F469A*")&&!cpuis("STM32F479A*") sif !cpuis("STM32F469V*")&&!cpuis("STM32F479V*") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "3,15,28,56,84,112,144,480" group.long 0x10++0x03 line.long 0x00 "ADC_SPMR2,ADC Sample Time Register 2" bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F469A*")||cpuis("STM32F479A*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,,,,,,17,18,?..." elif cpuis("STM32F469V*")||cpuis("STM32F479V*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,,,,17,18,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,,17,18,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end tree "ADC 2" base ad:0x40012100 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" group.long 0x00++0x03 line.long 0x00 "ADC_CR1,ADC Control Register 1" bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x00 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x00 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" textline " " sif cpuis("STM32F469A*")||cpuis("STM32F479A*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,?..." elif cpuis("STM32F469V*")||cpuis("STM32F479V*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..." else bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." endif if (((per.l(ad:0x40012100+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" sif !cpuis("STM32F469A*")&&!cpuis("STM32F479A*") sif !cpuis("STM32F469V*")&&!cpuis("STM32F479V*") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "3,15,28,56,84,112,144,480" group.long 0x10++0x03 line.long 0x00 "ADC_SPMR2,ADC Sample Time Register 2" bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F469A*")||cpuis("STM32F479A*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif cpuis("STM32F469V*")||cpuis("STM32F479V*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end tree "ADC 3" base ad:0x40012200 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" group.long 0x00++0x03 line.long 0x00 "ADC_CR1,ADC Control Register 1" bitfld.long 0x00 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x00 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x00 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x00 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x00 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x00 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x00 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x00 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x00 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" textline " " sif cpuis("STM32F469A*")||cpuis("STM32F479A*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,,,,,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,,,ADC_IN14,ADC_IN15,?..." elif cpuis("STM32F469V*")||cpuis("STM32F479V*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,,,,,,,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..." elif cpuis("STM32F469Z*")||cpuis("STM32F479Z*") bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,,,,,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." else bitfld.long 0x00 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." endif if (((per.l(ad:0x40012200+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CH1,TIM1_CH2,TIM1_CH3,TIM2_CH2,TIM2_CH3,TIM2_CH4,TIM2_TRGO,TIM3_CH1,TIM3_TRGO,TIM4_CH4,TIM5_CH1,TIM5_CH2,TIM5_CH3,TIM8_CH1,TIM8_TRGO,EXTI11" textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CH4,TIM1_TRGO,TIM2_CH1,TIM2_TRGO,TIM3_CH2,TIM3_CH4,TIM4_CH1,TIM4_CH2,TIM4_CH3,TIM4_TRGO,TIM5_CH4,TIM5_TRGO,TIM8_CH2,TIM8_CH3,TIM8_CH4,EXTI15" textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" sif !cpuis("STM32F469V*")&&!cpuis("STM32F479V*") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif !cpuis("STM32F469A*")&&!cpuis("STM32F479A*") bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "3,15,28,56,84,112,144,480" group.long 0x10++0x03 line.long 0x00 "ADC_SPMR2,ADC Sample Time Register 2" sif !cpuis("STM32F469V*")&&!cpuis("STM32F479V*") bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif !cpuis("STM32F469V*")&&!cpuis("STM32F479V*")&&!cpuis("STM32F469Z*")&&!cpuis("STM32F479Z*")&&!cpuis("STM32F469A*")&&!cpuis("STM32F479A*") bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "3,15,28,56,84,112,144,480" textline " " endif bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F469V*")||cpuis("STM32F479V*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,,,,,,,10,11,12,13,?..." elif cpuis("STM32F469Z*")||cpuis("STM32F479Z*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,12,13,14,15,?..." elif cpuis("STM32F469A*")||cpuis("STM32F479A*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,,,,,8,9,10,11,,,14,15,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end else tree "ADC 1" base ad:0x40012000 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" line.long 0x04 "ADC_CR1,ADC Control Register 1" bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" sif cpuis("STM32F410T*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,,ADC_IN2,ADC_IN3,,ADC_IN5,,,,,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410R*")||cpuis("STM32F412R*")||cpuis("STM32F412V*")||cpuis("STM32F412Z*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif (cpuis("STM32F411C?")||cpuis("STM32F401C?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..." elif (cpu()=="STM32F405O*"||cpu()=="STM32F415O*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..." elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..." elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..." else textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..." endif if (((per.l(ad:0x40012000+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,?..." bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,?..." bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?")) group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F412Z*")||cpuis("STM32F413M*")||cpu()=="STM32F423MH"||cpuis("STM32F413Z*")||cpu()=="STM32F423ZH") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")) bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpu()!="STM32F405OE"&&cpu()!="STM32F405OG"&&cpu()!="STM32F415OG"&&!cpuis("STM32F446M?")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif !cpuis("STM32F410T*")&&!cpuis("STM32F410C*")&&!cpuis("STM32F412C*")&&!cpuis("STM32F413C*")&&!(cpu()=="STM32F423CH") bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480" endif endif sif cpuis("STM32F410T*") group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480" else group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" endif textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F410T*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." elif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?")||cpuis("STM32F410R*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("STM32F405O*")||cpuis("STM32F415O*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) tree "ADC 2" base ad:0x40012100 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" line.long 0x04 "ADC_CR1,ADC Control Register 1" bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" sif cpuis("STM32F410T*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,,ADC_IN2,ADC_IN3,,ADC_IN5,,,,,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410R*")||cpuis("STM32F412R*")||cpuis("STM32F412V*")||cpuis("STM32F412Z*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif (cpuis("STM32F411C?")||cpuis("STM32F401C?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..." elif (cpu()=="STM32F405O*"||cpu()=="STM32F415O*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..." elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..." elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..." else textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..." endif if (((per.l(ad:0x40012100+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,?..." bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,?..." bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?")) group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F412Z*")||cpuis("STM32F413M*")||cpu()=="STM32F423MH"||cpuis("STM32F413Z*")||cpu()=="STM32F423ZH") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")) bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpu()!="STM32F405OE"&&cpu()!="STM32F405OG"&&cpu()!="STM32F415OG"&&!cpuis("STM32F446M?")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif !cpuis("STM32F410T*")&&!cpuis("STM32F410C*")&&!cpuis("STM32F412C*")&&!cpuis("STM32F413C*")&&!(cpu()=="STM32F423CH") bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480" endif endif sif cpuis("STM32F410T*") group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480" else group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" endif textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F410T*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." elif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?")||cpuis("STM32F410R*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("STM32F405O*")||cpuis("STM32F415O*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end sif (!cpuis("STM32F446M?")&&!cpuis("STM32F446R?")&&!cpuis("STM32F446V?")) tree "ADC 3" base ad:0x40012200 width 11. group.long 0x00++0x13 line.long 0x00 "ADC_SR,ADC Status Register" bitfld.long 0x00 5. " OVR ,Overrun" "Not occurred,Occurred" bitfld.long 0x00 4. " STRT ,Regular channel start flag" "Not started,Started" bitfld.long 0x00 3. " JSTRT ,Injected channel start flag" "Not started,Started" bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed" textline " " bitfld.long 0x00 1. " EOC ,Regular channel end of conversion" "Not completed,Completed" bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred" line.long 0x04 "ADC_CR1,ADC Control Register 1" bitfld.long 0x04 26. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24.--25. " RES ,Resolution" "12-bit,10-bit,8-bit,6-bit" bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled" bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled" textline " " bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH" bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled" bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled" bitfld.long 0x04 10. " JAUTO ,Automatic injected group conversion" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single" bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled" bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled" bitfld.long 0x04 6. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled" sif cpuis("STM32F410T*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,,ADC_IN2,ADC_IN3,,ADC_IN5,,,,,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,,,,,,,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif cpuis("STM32F410R*")||cpuis("STM32F412R*")||cpuis("STM32F412V*")||cpuis("STM32F412Z*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,?..." elif (cpuis("STM32F411C?")||cpuis("STM32F401C?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..." elif (cpu()=="STM32F405O*"||cpu()=="STM32F415O*") textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,?..." elif (cpuis("STM32F446M?")||cpuis("STM32F469V*")||cpuis("STM32F479V*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,?..." elif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F7??V?")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..." elif (cpuis("STM32F469Z*")||cpuis("STM32F479Z*")) textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,?..." else textline " " bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,ADC_IN18,ADC_IN19,ADC_IN20,ADC_IN21,ADC_IN22,ADC_IN23,?..." endif if (((per.l(ad:0x40012200+0x08))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" bitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,Start" bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " bitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,Start" bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "ADC_CR2,ADC Control Register 2" rbitfld.long 0x00 30. " SWSTART ,Start conversion of regular channels" "Reset,?..." bitfld.long 0x00 28.--29. " EXTEN ,External trigger enable for regular channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,,,,,,,,TIM5_CC1,TIM5_CC2,TIM5_CC3,,,EXTI11" else textline " " bitfld.long 0x00 24.--27. " EXTSEL ,External event select for regular group" "TIM1_CC1,TIM1_CC2,TIM1_CC3,TIM2_CC2,TIM2_CC3,TIM2_CC4,TIM2_TRGO,TIM3_CC1,TIM3_TRGO,TIM4_CC4,TIM5_CC1,TIM5_CC2,TIM5_CC3,TIM8_CC1,TIM8_TRGO,EXTI11" endif textline " " rbitfld.long 0x00 22. " JSWSTART ,Start conversion of injected channels" "Reset,?..." bitfld.long 0x00 20.--21. " JEXTEN ,External trigger enable for injected channels" "Disabled,Rising edge,Falling edge,Both" sif cpuis("STM32F411*")||cpuis("STM32F401*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,,,,EXTI15" elif cpuis("STM32F410*") textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,,,,,,,,,TIM5_CC4,TIM5_TRGO,,,,EXTI15" else textline " " bitfld.long 0x00 16.--19. " JEXTSEL ,External event select for injected group" "TIM1_CC4,TIM1_TRGO,TIM2_CC1,TIM2_TRGO2,TIM3_CC2,TIM3_CC4,TIM4_CC1,TIM4_CC2,TIM4_CC3,TIM4_TRGO,TIM5_CC4,TIM5_TRGO,TIM8_CC2,TIM8_CC3,TIM8_CC4,EXTI15" endif textline " " bitfld.long 0x00 11. " ALIGN ,Data alignment" "Right,Left" bitfld.long 0x00 10. " EOCS ,End of conversion selection" "Sequence,Conversion" bitfld.long 0x00 9. " DDS ,DMA disable selection" "Disabled,Enabled" bitfld.long 0x00 8. " DMA ,Direct memory access mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CONT ,Continuous conversion" "Single,Continuous" bitfld.long 0x00 0. " ADON ,A/D converter ON / OFF" "Disabled,Enabled" endif textline " " sif (!cpuis("STM32F411C?")&&!cpuis("STM32F401C?")) group.long 0x0C++0x03 line.long 0x00 "ADC_SMPR1,ADC Sample Time Register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif (cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")||cpuis("STM32F7??V?")||cpuis("STM32F412Z*")||cpuis("STM32F413M*")||cpu()=="STM32F423MH"||cpuis("STM32F413Z*")||cpu()=="STM32F423ZH") bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")) bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " elif (cpu()!="STM32F405OE"&&cpu()!="STM32F405OG"&&cpu()!="STM32F415OG"&&!cpuis("STM32F446M?")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x00 24.--26. " SMP18 ,Channel 18 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 sample time selection" "3,15,28,56,84,112,144,480" textline " " endif sif !cpuis("STM32F410T*")&&!cpuis("STM32F410C*")&&!cpuis("STM32F412C*")&&!cpuis("STM32F413C*")&&!(cpu()=="STM32F423CH") bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 sample time selection" "3,15,28,56,84,112,144,480" endif endif sif cpuis("STM32F410T*") group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 sample time selection" "3,15,28,56,84,112,144,480" else group.long 0x10++0x03 line.long 0x00 "ADC_SMPR2,ADC Sample Time Register 2" bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 sample time selection" "3,15,28,56,84,112,144,480" textline " " bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "3,15,28,56,84,112,144,480" bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "3,15,28,56,84,112,144,480" endif textline " " group.long 0x14++0x03 line.long 0x00 "ADC_JOFR1,ADC Injected Channel Data Offset Register 1" hexmask.long.word 0x00 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1" group.long 0x18++0x03 line.long 0x00 "ADC_JOFR2,ADC Injected Channel Data Offset Register 2" hexmask.long.word 0x00 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2" group.long 0x1C++0x03 line.long 0x00 "ADC_JOFR3,ADC Injected Channel Data Offset Register 3" hexmask.long.word 0x00 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3" group.long 0x20++0x03 line.long 0x00 "ADC_JOFR4,ADC Injected Channel Data Offset Register 4" hexmask.long.word 0x00 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4" textline " " group.long 0x24++0x07 line.long 0x00 "ADC_HTR,ADC Watchdog High Threshold Register" hexmask.long.word 0x00 0.--11. 1. " HT ,Analog watchdog higher threshold" line.long 0x04 "ADC_LTR,ADC Watchdog Low Threshold Register" hexmask.long.word 0x04 0.--11. 1. " LT ,Analog watchdog lower threshold" sif cpuis("STM32F410T*") group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,,2,3,,5,,,,,,,,,,,16,17,18,?..." elif cpuis("STM32F410C*")||cpuis("STM32F412C*")||cpuis("STM32F413C*")||cpu()=="STM32F423CH" group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,,,,,,,16,17,18,?..." elif (cpuis("STM32F446*")||cpuis("STM32F411R?")||cpuis("STM32F411V?")||cpuis("STM32F411C?")||cpuis("STM32F401R?")||cpuis("STM32F401V?")||cpuis("STM32F401C?")||cpuis("STM32F410R*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." elif (cpuis("STM32F427A*")||cpuis("STM32F429Z*")||cpuis("STM32F429N*")||cpuis("STM32F429I*")||cpuis("STM32F429B*")||cpuis("STM32F429A*")||cpuis("STM32F437AI")||cpuis("STM32F439AI")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("STM32F20?R*")||cpuis("STM32F21?R*")||cpuis("STM32F205V*")||cpuis("STM32F207V*")||cpuis("STM32F215V*")||cpuis("STM32F4??R*")||cpuis("STM32F4??V*")||cpuis("STM32F469I*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("STM32F405O*")||cpuis("STM32F415O*")) group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected Sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,?..." else group.long 0x2C++0x0F line.long 0x00 "ADC_SQR1,ADC Regular Sequence Register 1" bitfld.long 0x00 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x00 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x00 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x04 "ADC_SQR2,ADC Regular Sequence Register 2" bitfld.long 0x04 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x04 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x04 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x08 "ADC_SQR3,ADC Regular Sequence Register 3" bitfld.long 0x08 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 10.--14. " SQ3 ,3rd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x08 5.--9. " SQ2 ,2nd conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x08 0.--4. " SQ1 ,1st conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." line.long 0x0C "ADC_JSQR,ADC Injected Sequence Register" bitfld.long 0x0C 20.--21. " JL ,Injected sequence length" "1,2,3,4" bitfld.long 0x0C 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 10.--14. " JSQ3 ,3rd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.long 0x0C 5.--9. " JSQ2 ,2nd conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." textline " " bitfld.long 0x0C 0.--4. " JSQ1 ,1st conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." endif rgroup.long 0x3C++0x03 line.long 0x00 "ADC_JDR1,ADC Injected Data Register 1" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x40++0x03 line.long 0x00 "ADC_JDR2,ADC Injected Data Register 2" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x44++0x03 line.long 0x00 "ADC_JDR3,ADC Injected Data Register 3" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x48++0x03 line.long 0x00 "ADC_JDR4,ADC Injected Data Register 4" hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data" rgroup.long 0x4C++0x03 line.long 0x00 "ADC_DR,ADC Regular Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data" width 0x0B tree.end endif endif endif tree.end sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F412*")) tree "DAC (Digital-to-Analog Converter)" sif cpuis("STM32F410*") base ad:0x40007400 width 13. if (((per.l(ad:0x40007400))&0x4)==0x04) if (((per.l(ad:0x40007400))&0xC0)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" ",,,TIM5 TRGO,,,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC0)==0x40) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" ",,,TIM5 TRGO,,,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" ",,,TIM5 TRGO,,,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" endif wgroup.long 0x04++0x03 line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register" bitfld.long 0x00 0. " SWTRIG1 ,DAC channel 1 software trigger" "Disable,Enable" group.long 0x08++0x0B line.long 0x00 "DAC_DHR12R1,DAC Channel 1 12-bit Right-aligned Data Holding Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right-aligned data" line.long 0x04 "DAC_DHR12L1,DAC Channel 1 12-bit Left-aligned Data Holding Register" hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data" line.long 0x08 "DAC_DHR8R1,DAC Channel 1 8-bit Right-aligned Data Holding Register" hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data" rgroup.long 0x2C++0x03 line.long 0x00 "DAC_DOR1,DAC Channel 1 Data Output Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel 1 data output" group.long 0x34++0x03 line.long 0x00 "DAC_SR,DAC Status Register" bitfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error" width 0x0B elif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") base ad:0x40007400 width 13. if (((per.l(ad:0x40007400))&0x40004)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0x40004)==0x00004) if (((per.l(ad:0x40007400))&0xC0)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC0)==0x40) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" endif elif (((per.l(ad:0x40007400))&0x40004)==0x40000) if (((per.l(ad:0x40007400))&0xC00000)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC00000)==0x400000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" textline " " bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40007400))&0xC000C0)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==0x40) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==(0x80||0xC0)) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==0x400000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==0x400040) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==(0x400080||0x4000C0)) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==(0x800000||0xC00000)) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" elif (((per.l(ad:0x40007400))&0xC000C0)==(0x800040||0xC00040)) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask selector" "LFSR[0] unmasked,LFSR[1:0] unmasked,LFSR[2:0] unmasked,LFSR[3:0] unmasked,LFSR[4:0] unmasked,LFSR[5:0] unmasked,LFSR[6:0] unmasked,LFSR[7:0] unmasked,LFSR[8:0] unmasked,LFSR[9:0] unmasked,LFSR[10:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked,LFSR[11:0] unmasked" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC Control Register" bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 , DAC channel 2 DMA enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel 2 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel 1 DMA underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 , DAC channel 1 DMA enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel 1 noise/triangle wave generation disabled" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "TIM6 TRGO,TIM8 TRGO,TIM7 TRGO,TIM5 TRGO,TIM2 TRGO,TIM4 TRGO,EXTI line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled" endif endif wgroup.long 0x04++0x03 line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register" bitfld.long 0x00 1. " SWTRIG2 ,DAC channel 2 software trigger" "Disable,Enable" textline " " bitfld.long 0x00 0. " SWTRIG1 ,DAC channel 1 software trigger" "Disable,Enable" group.long 0x08++0x23 line.long 0x00 "DAC_DHR12R1,DAC Channel 1 12-bit Right-aligned Data Holding Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right-aligned data" line.long 0x04 "DAC_DHR12L1,DAC Channel 1 12-bit Left-aligned Data Holding Register" hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data" line.long 0x08 "DAC_DHR8R1,DAC Channel 1 8-bit Right-aligned Data Holding Register" hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data" line.long 0x0C "DAC_DHR12R2,DAC Channel 2 12-bit Right-aligned Data Holding Register" hexmask.long.word 0x0C 0.--11. 1. " DACC2DHR ,DAC channel 2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,DAC Channel 2 12-bit Left-aligned Data Holding Register" hexmask.long.word 0x10 4.--15. 1. " DACC2DHR ,DAC channel 2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,DAC Channel 2 8-bit Right-aligned Data Holding Register" hexmask.long.byte 0x14 0.--7. 1. " DACC2DHR ,DAC channel 1 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit Right-aligned Data Holding Register" hexmask.long.word 0x18 16.--27. 1. " DACC2DHR ,DAC channel 2 12-bit right-aligned data" textline " " hexmask.long.word 0x18 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,Dual DAC 12-bit Left-aligned Data Holding Register" hexmask.long.word 0x1C 20.--31. 1. " DACC2DHR ,DAC channel 2 12-bit left-aligned data" textline " " hexmask.long.word 0x1C 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,Dual DAC 8-bit Right-aligned Data Holding Register" hexmask.long.byte 0x20 8.--15. 1. " DACC2DHR ,DAC channel 2 8-bit right-aligned data" textline " " hexmask.long.byte 0x20 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data" rgroup.long 0x2C++0x07 line.long 0x00 "DAC_DOR1,DAC Channel 1 Data Output Register" hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel 1 data output" line.long 0x04 "DAC_DOR2,DAC Channel 2 Data Output Register" hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,DAC channel 2 data output" group.long 0x34++0x03 line.long 0x00 "DAC_SR,DAC Status Register" bitfld.long 0x00 29. " DMAUDR2 ,DAC channel 2 DMA underrun flag" "No error,Error" textline " " bitfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error" width 0x0B else base ad:0x40007400 width 13. if ((per.l(ad:0x40007400)&0x40004)==0x40004) if ((per.l(ad:0x40007400)&0xC00000)==0x00) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC control register" bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC Channel 2 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,Channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled" textline " " elif ((per.l(ad:0x40007400)&0x40004)==0x00004) elif ((per.l(ad:0x40007400)&0xC00000)==0xC00000) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC control register" bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask/amplitude selector" "Bit[0],Bits[1:0],Bits[2:0],Bits[3:0],Bits[4:0],Bits[5:0],Bits[6:0],Bits[7:0],Bits[8:0],Bits[9:0],Bits[10:0],Bits[11:0],Bits[11:0],Bits[11:0],Bits[11:0],Bits[11:0]" bitfld.long 0x00 18. " TEN2 ,DAC Channel 2 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask/amplitude selector" "Bit[0],Bits[1:0],Bits[2:0],Bits[3:0],Bits[4:0],Bits[5:0],Bits[6:0],Bits[7:0],Bits[8:0],Bits[9:0],Bits[10:0],Bits[11:0],Bits[11:0],Bits[11:0],Bits[11:0],Bits[11:0]" bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 3.--5. " TSEL1 ,Channel 1 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger" bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled" elif ((per.l(ad:0x40007400)&0x40004)==0x40000) elif ((per.l(ad:0x40007400)&0xC00000)==0x04) group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC control regi ster" bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle" textline " " bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger" bitfld.long 0x00 18. " TEN2 ,DAC Channel 2 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled" textline " " else else group.long 0x00++0x03 line.long 0x00 "DAC_CR,DAC control register" bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 18. " TEN2 ,DAC Channel 2 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes" bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095" bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes" bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled" endif endif wgroup.long 0x04++0x03 line.long 0x00 "DAC_SWTRIGR,DAC software trigger register" bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disable,Enable" bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disable,Enable" group.long 0x08++0x23 line.long 0x00 "DAC_DHR12R1,Channel 1 12-bit right-aligned data" hexmask.long.word 0x00 0.--11. 1. " DACC1DHR , 11:0 Channel 1 12-bit right-aligned data" line.long 0x04 "DAC_DHR12L1,Channel 1 12-bit left-aligned data holding register" hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,Channel 1 12-bit left-aligned data" line.long 0x08 "DAC_DHR8R1,Channel 1 8-bit right aligned data holding register" hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,Channel 1 8-bit right-aligned data" line.long 0x0C "DAC_DHR12R2,Channel 2 12-bit right aligned data holding register" hexmask.long.word 0x0C 0.--11. 1. " DACC2DHR ,Channel 2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,Channel 2 12-bit left aligned data holding register" hexmask.long.word 0x10 4.--15. 1. " DACC2DHR ,Channel 2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,Channel 2 8-bit right-aligned data holding register" hexmask.long.byte 0x14 0.--7. 1. " DACC2DHR ,Channel 2 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual 12-bit right-aligned data holding register" hexmask.long.word 0x18 16.--27. 1. " DACC2DHR ,Channel 2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. " DACC1DHR ,Channel 1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,DUAL 12-bit left aligned data holding register" hexmask.long.word 0x1C 20.--31. 1. " DACC2DHR ,Channel 2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. " DACC1DHR ,Channel 1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,DUAL 8-bit right aligned data holding register" hexmask.long.byte 0x20 8.--15. 1. " DACC2DHR ,Channel 2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. " DACC1DHR ,Channel 1 8-bit right-aligned data" rgroup.long 0x2C++0x07 line.long 0x00 "DAC_DOR1,DAC channel1 data output register" hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,Channel 1 data output" line.long 0x04 "DAC_DOR2,DAC channel2 data output register" hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,Channel 2 data output" group.long 0x34++0x03 line.long 0x00 "DAC_SR,Status register" eventfld.long 0x00 29. " DMAUDR2 ,Channel 2 DMA underrun flag" "No error,Error" eventfld.long 0x00 13. " DMAUDR1 ,Channel 1 DMA underrun flag" "No error,Error" width 0x0B endif tree.end endif sif (cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) tree "DCMI (Digital Camera Interface)" base ad:0x50050000 width 13. sif (cpuis("STM32F446*")||cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")) if (((per.l(ad:0x50050000)&0x08))==0x08) if (((per.l(ad:0x50050000)&0xC00))==0x00) group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even" bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2" bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even" textline " " bitfld.long 0x00 16.--17. " BSM ,Byte select mode" "All data,Every other,1B out of 4B,2B out of 4B" textline " " bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" else group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even" bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2" bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even" textline " " textline " " bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" endif else if (((per.l(ad:0x50050000)&0xC00))==0x00) group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even" bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2" bitfld.long 0x00 18. " OEBS ,Odd/even byte select (byte select start)" "Odd,Even" textline " " bitfld.long 0x00 16.--17. " BSM ,Byte select mode" "All data,Every other,1B out of 4B,2B out of 4B" textline " " bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" textline " " bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "HSYNC/VSYNC signals,Synchronization codes" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" else group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 20. " OELS ,Odd/even line select (line select start)" "Odd,Even" bitfld.long 0x00 19. " LSM ,Line select mode" "All lines,1 out of 2" bitfld.long 0x00 18. " OEBS ,odd/even byte select (byte select start)" "Odd,Even" textline " " textline " " bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" textline " " bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "HSYNC/VSYNC signals,Synchronization codes" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" endif endif else if (((per.l(ad:0x50050000)&0x08))==0x08) group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" else group.long 0x00++0x3 line.long 0x00 "DCMI_CR,DCMI Control Register 1" bitfld.long 0x00 14. " ENABLE ,DCMI enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " EDM ,Extended data mode (data per pixel clock)" "8-bit,10-bit,12-bit,14-bit" bitfld.long 0x00 8.--9. " FCRC ,Frame capture rate control" "Capture all frames,Capture every alternate frame,Capture one frame in 4 frames,?..." textline " " bitfld.long 0x00 7. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x00 6. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" textline " " bitfld.long 0x00 5. " PCKPOL ,Pixel clock polarity" "Falling edge,Rising edge" bitfld.long 0x00 4. " ESS ,Embedded synchronization select" "HSYNC/VSYNC signals,Synchronization codes" textline " " bitfld.long 0x00 3. " JPEG ,JPEG format" "Uncompressed video,Compressed video" bitfld.long 0x00 2. " CROP ,Crop feature" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CM ,Capture mode" "Continuous grab,Snapshot" bitfld.long 0x00 0. " CAPTURE ,Capture enable" "Disabled,Enabled" endif endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "DCMI_SR,DCMI Status Register" bitfld.long 0x00 2. " FNE ,FIFO not empty" "Empty,Not empty" bitfld.long 0x00 1. " VSYNC ,VSYNC pin state" "Active frame,Synchronization between frames" textline " " bitfld.long 0x00 0. " HSYNC ,HSYNC pin state" "Active line,Synchronization between lines" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x50050000)&0x10))==0x10) rgroup.long 0x08++0x03 line.long 0x00 "DCMI_RIS,DCMI Raw Interrupt Status Register" bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " ERR_RIS ,Synchronization error raw interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_RIS ,Overrun raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt" else rgroup.long 0x08++0x03 line.long 0x00 "DCMI_RIS,DCMI Raw Interrupt Status Register" bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_RIS ,Overrrun raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt" endif else rgroup.long 0x08++0x03 line.long 0x00 "DCMI_RIS,DCMI Raw Interrupt Status Register" bitfld.long 0x00 4. " LINE_RIS ,Line raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_RIS ,VSYNC raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " ERR_RIS ,Synchronization error raw interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_RIS ,Overrrun raw interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_RIS ,Capture complete raw interrupt status" "No interrupt,Interrupt" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x50050000)&0x10))==0x10) group.long 0x0C++0x3 line.long 0x00 "DCMI_IER,DCMI Interrupt Enable Register" bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ERR_IE ,Synchronization error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled" else group.long 0x0C++0x3 line.long 0x00 "DCMI_IER,DCMI Interrupt Enable Register" bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled" endif else group.long 0x0C++0x3 line.long 0x00 "DCMI_IER,DCMI Interrupt Enable Register" bitfld.long 0x00 4. " LINE_IE ,Line interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " VSYNC_IE ,VSYNC interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " ERR_IE ,Synchronization error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " OVR_IE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRAME_IE ,Capture complete interrupt enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x50050000)&0x10))==0x10) rgroup.long 0x10++0x3 line.long 0x00 "DCMI_MIS,DCMI Masked Interrupt Status Register" bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " ERR_MIS ,Synchronization error masked interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt" else rgroup.long 0x10++0x3 line.long 0x00 "DCMI_MIS,DCMI Masked Interrupt Status Register" bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt" endif else rgroup.long 0x10++0x3 line.long 0x00 "DCMI_MIS,DCMI Masked Interrupt Status Register" bitfld.long 0x00 4. " LINE_MIS ,Line masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 3. " VSYNC_MIS ,VSYNC masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " ERR_MIS ,Synchronization error masked interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVR_MIS ,Overrun masked interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " FRAME_MIS ,Capture complete masked interrupt status" "No interrupt,Interrupt" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x50050000)&0x10))==0x10) wgroup.long 0x14++0x3 line.long 0x00 "DCMI_ICR,DCMI Interrupt Clear Register" bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear" bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear" bitfld.long 0x00 2. " ERR_ISC ,Synchronization error interrupt status clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " OVR_ISC ,Overrun interrupt status clear" "No effect,Clear" bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear" else wgroup.long 0x14++0x3 line.long 0x00 "DCMI_ICR,DCMI Interrupt Clear Register" bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear" bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " OVR_ISC ,Overrun interrupt status clear" "No effect,Clear" bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear" endif else wgroup.long 0x14++0x3 line.long 0x00 "DCMI_ICR,DCMI Interrupt Clear Register" bitfld.long 0x00 4. " LINE_ISC ,Line interrupt status clear" "No effect,Clear" bitfld.long 0x00 3. " VSYNC_ISC ,VSYNC interrupt status clear" "No effect,Clear" bitfld.long 0x00 2. " ERR_ISC ,Synchronization error interrupt status clear" "No effect,Clear" textline " " bitfld.long 0x00 1. " OVR_ISC ,Overrun Interrupt Status Clear" "No effect,Clear" bitfld.long 0x00 0. " FRAME_ISC ,Capture complete interrupt status clear" "No effect,Clear" endif group.long 0x18++0xF line.long 0x00 "DCMI_ESCR,DCMI Embedded Synchronization Code Register" hexmask.long.byte 0x00 24.--31. 1. " FEC ,Frame end delimiter code" hexmask.long.byte 0x00 16.--23. 1. " LEC ,Line end delimiter code" textline " " hexmask.long.byte 0x00 8.--15. 1. " LSC ,Line start delimiter code" hexmask.long.byte 0x00 0.--7. 1. " FSC ,Frame start delimiter code" line.long 0x04 "DCMI_ESUR,DCMI Embedded Synchronization Unmask Register" bitfld.long 0x04 31. " FEU ,Frame end delimiter unmask [7]" "0,1" bitfld.long 0x04 30. ",Frame end delimiter unmask [6]" "0,1" bitfld.long 0x04 29. ",Frame end delimiter unmask [5]" "0,1" bitfld.long 0x04 28. ",Frame end delimiter unmask [4]" "0,1" bitfld.long 0x04 27. ",Frame end delimiter unmask [3]" "0,1" bitfld.long 0x04 26. ",Frame end delimiter unmask [2]" "0,1" bitfld.long 0x04 25. ",Frame end delimiter unmask [1]" "0,1" bitfld.long 0x04 24. ",Frame end delimiter unmask [0]" "0,1" bitfld.long 0x04 23. " LEU ,Line end delimiter unmask [7]" "0,1" bitfld.long 0x04 22. ",Line end delimiter unmask [6]" "0,1" bitfld.long 0x04 21. ",Line end delimiter unmask [5]" "0,1" bitfld.long 0x04 20. ",Line end delimiter unmask [4]" "0,1" bitfld.long 0x04 19. ",Line end delimiter unmask [3]" "0,1" bitfld.long 0x04 18. ",Line end delimiter unmask [2]" "0,1" bitfld.long 0x04 17. ",Line end delimiter unmask [1]" "0,1" bitfld.long 0x04 16. ",Line end delimiter unmask [0]" "0,1" textline " " bitfld.long 0x04 15. " LSU ,Line start delimiter unmask [7]" "0,1" bitfld.long 0x04 14. ",Line start delimiter unmask [6]" "0,1" bitfld.long 0x04 13. ",Line start delimiter unmask [5]" "0,1" bitfld.long 0x04 12. ",Line start delimiter unmask [4]" "0,1" bitfld.long 0x04 11. ",Line start delimiter unmask [3]" "0,1" bitfld.long 0x04 10. ",Line start delimiter unmask [2]" "0,1" bitfld.long 0x04 9. ",Line start delimiter unmask [1]" "0,1" bitfld.long 0x04 8. ",Line start delimiter unmask [0]" "0,1" bitfld.long 0x04 7. " FSU ,Frame start delimiter unmask [7]" "0,1" bitfld.long 0x04 6. ",Frame start delimiter unmask [6]" "0,1" bitfld.long 0x04 5. ",Frame start delimiter unmask [5]" "0,1" bitfld.long 0x04 4. ",Frame start delimiter unmask [4]" "0,1" bitfld.long 0x04 3. ",Frame start delimiter unmask [3]" "0,1" bitfld.long 0x04 2. ",Frame start delimiter unmask [2]" "0,1" bitfld.long 0x04 1. ",Frame start delimiter unmask [1]" "0,1" bitfld.long 0x04 0. ",Frame start delimiter unmask [0]" "0,1" line.long 0x08 "DCMI_CWSTRT,DCMI Crop Window Start" hexmask.long.word 0x08 16.--28. 1. " VST ,Vertical start line count" hexmask.long.word 0x08 0.--13. 1. " HOFFCNT ,Horizontal offset count" line.long 0x0C "DCMI_CWSIZE,DCMI Crop Window Size" hexmask.long.word 0x0C 16.--29. 1. " VLINE ,Vertical line count" hexmask.long.word 0x0C 0.--13. 1. " CAPCNT ,Capture count" rgroup.long 0x28++0x3 line.long 0x00 "DCMI_DR,DCMI Data Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Data byte 3" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Data byte 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Data byte 1" hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Data byte 0" width 0xB tree.end endif sif (cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F469*")||cpuis("STM32F479*")) tree "LCD-TFT (LCD-TFT Controller)" base ad:0x40016800 width 14. group.long 0x08++0x13 line.long 0x00 "LTDC_SSCR,LTDC Synchronization Size Configuration Register" hexmask.long.word 0x00 16.--27. 1. " HSW ,Horizontal synchronization width" hexmask.long.word 0x00 0.--10. 1. " VSH ,Vertical synchronization height" line.long 0x04 "LTDC_BPCR,LTDC Back Porch Configuration Register" hexmask.long.word 0x04 16.--27. 1. " AHBP ,Accumulated horizontal back porch" hexmask.long.word 0x04 0.--10. 1. " AVBP ,Accumulated vertical back porch" line.long 0x08 "LTDC_AWCR,LTDC Active Width Configuration Register" hexmask.long.word 0x08 16.--27. 1. " AAW ,Accumulated active width" hexmask.long.word 0x08 0.--10. 1. " AAH ,Accumulated active height" line.long 0x0C "LTDC_TWCR,LTDC Total Width Configuration Register" hexmask.long.word 0x0C 16.--27. 1. " TOTALW ,Total width" hexmask.long.word 0x0C 0.--10. 1. " TOTALH ,Total height" line.long 0x10 "LTDC_GCR,LTDC Global Control Register" bitfld.long 0x10 31. " HSPOL ,Horizontal synchronization polarity" "Active low,Active high" bitfld.long 0x10 30. " VSPOL ,Vertical synchronization polarity" "Active low,Active high" bitfld.long 0x10 29. " DEPOL ,Data enable polarity" "Active low,Active high" textline " " bitfld.long 0x10 28. " PCPOL ,Pixel clock polarity" "Normal,Inverted" bitfld.long 0x10 16. " DEN ,Dither enable" "Disabled,Enabled" rbitfld.long 0x10 12.--14. " DRW ,Dither red width" "0,1,2,3,4,5,6,7" textline " " rbitfld.long 0x10 8.--10. " DGW ,Dither green width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 4.--6. " DBW ,Dither blue width" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. " LTDCEN ,LCD-TFT controller enable" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "LTDC_SRCR,LTDC Shadow Reload Configuration Register" bitfld.long 0x00 1. " VBR ,Vertical blanking reload" "No effect,Reload" bitfld.long 0x00 0. " IMR ,Immediate reload" "No effect,Reload" group.long 0x2C++0x03 line.long 0x00 "LTDC_BCCR,LTDC Background Color Configuration Register" hexmask.long.byte 0x00 16.--23. 1. " BCRED ,Background color red value" hexmask.long.byte 0x00 8.--15. 1. " BCGREEN ,Background color green value" hexmask.long.byte 0x00 0.--7. 1. " BCBLUE ,Background color blue value" group.long 0x34++0x03 line.long 0x00 "LTDC_IER,LTDC Interrupt Enable Register" bitfld.long 0x00 3. " RRIE ,Register reload interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " TERRIE ,Transfer error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FUIE ,FIFO underrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LIE ,Line interrupt enable" "Disabled,Enabled" rgroup.long 0x38++0x03 line.long 0x00 "LTDC_ISR,LTDC Interrupt Status Register" bitfld.long 0x00 3. " RRIF ,Register reload interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " TERRIF ,Transfer error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 1. " FUIF ,FIFO underrun interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " LIF ,Line interrupt flag" "No interrupt,Interrupt" wgroup.long 0x3C++0x03 line.long 0x00 "LTDC_ICR,LTDC Interrupt Clear Register" bitfld.long 0x00 3. " CRRIF ,Register reload interrupt flag clear" "No effect,Clear" bitfld.long 0x00 2. " CTERRIF ,Transfer error interrupt flag clear" "No effect,Clear" bitfld.long 0x00 1. " CFUIF ,FIFO underrun interrupt flag clear" "No effect,Clear" textline " " bitfld.long 0x00 0. " CLIF , Line interrupt flag clear" "No effect,Clear" group.long 0x40++0x03 line.long 0x00 "LTDC_LIPCR,LTDC Line Interrupt Position Configuration Register" hexmask.long.word 0x00 0.--10. 1. " LIPOS ,Line interrupt position" rgroup.long 0x44++0x07 line.long 0x00 "LTDC_CPSR,LTDC Current Position Status Register" hexmask.long.word 0x00 16.--31. 1. " CXPOS ,Current X position" hexmask.long.word 0x00 0.--15. 1. " CYPOS ,Current Y position" line.long 0x04 "LTDC_CDSR,LTDC Current Display Status Register" bitfld.long 0x04 3. " HSYNCS ,Horizontal synchronization display status" "Low,High" bitfld.long 0x04 2. " VSYNCS ,Vertical synchronization display status" "Low,High" textline " " bitfld.long 0x04 1. " HDES ,Horizontal data enable display status" "Low,High" bitfld.long 0x04 0. " VDES ,Vertical data enable display status" "Low,High" tree "Layer 1 Registers" group.long (0x84+0x0)++0x1F line.long 0x00 "LTDC_L1CR,LTDC Layer 1 Control Register" bitfld.long 0x00 4. " CLUTEN ,Color look-up table enable" "Disabled,Enabled" bitfld.long 0x00 1. " COLKEN ,Color keying enable" "Disabled,Enabled" bitfld.long 0x00 0. " LEN ,Layer enable" "Disabled,Enabled" line.long 0x04 "LTDC_L1WHPCR,LTDC Layer 1 Window Horizontal Position Configuration Register" hexmask.long.word 0x04 16.--27. 1. " WHSPPOS ,Window horizontal stop position" hexmask.long.word 0x04 0.--11. 1. " WHSTPOS ,Window horizontal start position" line.long 0x08 "LTDC_L1WVPCR,LTDC Layer 1 Window Verical Position Configuration Register" hexmask.long.word 0x08 16.--26. 1. " WVSPPOS ,Window verical stop position" hexmask.long.word 0x08 0.--10. 1. " WVSTPOS ,Window verical start position" line.long 0x0C "LTDC_L1CKCR,LTDC Layer 1 Color Keying Configuration Register" hexmask.long.byte 0x0C 16.--23. 1. " CKRED ,Color key red value" hexmask.long.byte 0x0C 8.--15. 1. " CKGREEN ,Color key green value" hexmask.long.byte 0x0C 0.--7. 1. " CKBLUE ,Color key blue value" line.long 0x10 "LTDC_L1PFCR,LTDC Layer 1 Pixel Format Configuration register" bitfld.long 0x10 0.--2. " PF ,Pixel format" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88" line.long 0x14 "LTDC_L1CACR,LTDC Layer 1 Constant Alpha Configuration Register" hexmask.long.byte 0x14 0.--7. 1. " CONSTA ,Constant alpha" line.long 0x18 "LTDC_L1DCCR,LTDC Layer 1 Default Color Configuration Register" hexmask.long.byte 0x18 24.--31. 1. " DCALPHA ,Default color alpha" hexmask.long.byte 0x18 16.--23. 1. " DCRED ,Default color red" hexmask.long.byte 0x18 8.--15. 1. " DCGREEN ,Default color green" textline " " hexmask.long.byte 0x18 0.--7. 1. " DCBLUE ,Default color blue" textline " " line.long 0x1C "LTDC_L1BFCR,LTDC Layer 1 Blending Factors Configuration Register" bitfld.long 0x1C 8.--10. " BF1 ,Blending factor 1" ",,,,Constant Alpha,,Pixel Alpha x Constant Alpha,?..." textline " " bitfld.long 0x1C 0.--2. " BF2 ,Blending factor 2" ",,,,,1 - Constant Alpha,,1 - (Pixel Alpha x Constant Alpha)" textline " " group.long (0xAC+0x0)++0x0B line.long 0x00 "LTDC_L1CFBAR,LTDC Layer 1 Color Frame Buffer Address Register" line.long 0x04 "LTDC_L1CFBLR,LTDC Layer 1 Color Frame Buffer Length Register" hexmask.long.word 0x04 16.--28. 1. " CFBP ,Color frame buffer pitch in bytes" hexmask.long.word 0x04 0.--12. 1. " CFBLL ,Color frame buffer line length" line.long 0x08 "LTDC_L1CFBLNR,LTDC Layer 1 ColorFrame Buffer Line Number Register" hexmask.long.word 0x08 0.--10. 1. " CFBLNBR ,Frame buffer line number" if (((per.l(ad:0x40016800+0x84+0x0+0x10))&0x07)>=0x05) wgroup.long (0xC4+0x0)++0x03 line.long 0x00 "LTDC_L1CLUTWR,LTDC Layer 1 CLUT Write Register" hexmask.long.byte 0x00 24.--31. 1. " CLUTADD ,CLUT address" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" textline " " hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" else hgroup.long (0xC4+0x0)++0x03 hide.long 0x00 "LTDC_L1CLUTWR,LTDC Layer 1 CLUT Write Register" endif tree.end tree "Layer 2 Registers" group.long (0x84+0x80)++0x1F line.long 0x00 "LTDC_L2CR,LTDC Layer 2 Control Register" bitfld.long 0x00 4. " CLUTEN ,Color look-up table enable" "Disabled,Enabled" bitfld.long 0x00 1. " COLKEN ,Color keying enable" "Disabled,Enabled" bitfld.long 0x00 0. " LEN ,Layer enable" "Disabled,Enabled" line.long 0x04 "LTDC_L2WHPCR,LTDC Layer 2 Window Horizontal Position Configuration Register" hexmask.long.word 0x04 16.--27. 1. " WHSPPOS ,Window horizontal stop position" hexmask.long.word 0x04 0.--11. 1. " WHSTPOS ,Window horizontal start position" line.long 0x08 "LTDC_L2WVPCR,LTDC Layer 2 Window Verical Position Configuration Register" hexmask.long.word 0x08 16.--26. 1. " WVSPPOS ,Window verical stop position" hexmask.long.word 0x08 0.--10. 1. " WVSTPOS ,Window verical start position" line.long 0x0C "LTDC_L2CKCR,LTDC Layer 2 Color Keying Configuration Register" hexmask.long.byte 0x0C 16.--23. 1. " CKRED ,Color key red value" hexmask.long.byte 0x0C 8.--15. 1. " CKGREEN ,Color key green value" hexmask.long.byte 0x0C 0.--7. 1. " CKBLUE ,Color key blue value" line.long 0x10 "LTDC_L2PFCR,LTDC Layer 2 Pixel Format Configuration register" bitfld.long 0x10 0.--2. " PF ,Pixel format" "ARGB8888,RGB888,RGB565,ARGB1555,ARGB4444,L8,AL44,AL88" line.long 0x14 "LTDC_L2CACR,LTDC Layer 2 Constant Alpha Configuration Register" hexmask.long.byte 0x14 0.--7. 1. " CONSTA ,Constant alpha" line.long 0x18 "LTDC_L2DCCR,LTDC Layer 2 Default Color Configuration Register" hexmask.long.byte 0x18 24.--31. 1. " DCALPHA ,Default color alpha" hexmask.long.byte 0x18 16.--23. 1. " DCRED ,Default color red" hexmask.long.byte 0x18 8.--15. 1. " DCGREEN ,Default color green" textline " " hexmask.long.byte 0x18 0.--7. 1. " DCBLUE ,Default color blue" textline " " line.long 0x1C "LTDC_L2BFCR,LTDC Layer 2 Blending Factors Configuration Register" bitfld.long 0x1C 8.--10. " BF1 ,Blending factor 1" ",,,,Constant Alpha,,Pixel Alpha x Constant Alpha,?..." textline " " bitfld.long 0x1C 0.--2. " BF2 ,Blending factor 2" ",,,,,1 - Constant Alpha,,1 - (Pixel Alpha x Constant Alpha)" textline " " group.long (0xAC+0x80)++0x0B line.long 0x00 "LTDC_L2CFBAR,LTDC Layer 2 Color Frame Buffer Address Register" line.long 0x04 "LTDC_L2CFBLR,LTDC Layer 2 Color Frame Buffer Length Register" hexmask.long.word 0x04 16.--28. 1. " CFBP ,Color frame buffer pitch in bytes" hexmask.long.word 0x04 0.--12. 1. " CFBLL ,Color frame buffer line length" line.long 0x08 "LTDC_L2CFBLNR,LTDC Layer 2 ColorFrame Buffer Line Number Register" hexmask.long.word 0x08 0.--10. 1. " CFBLNBR ,Frame buffer line number" if (((per.l(ad:0x40016800+0x84+0x80+0x10))&0x07)>=0x05) wgroup.long (0xC4+0x80)++0x03 line.long 0x00 "LTDC_L2CLUTWR,LTDC Layer 2 CLUT Write Register" hexmask.long.byte 0x00 24.--31. 1. " CLUTADD ,CLUT address" hexmask.long.byte 0x00 16.--23. 1. " RED ,Red value" hexmask.long.byte 0x00 8.--15. 1. " GREEN ,Green value" textline " " hexmask.long.byte 0x00 0.--7. 1. " BLUE ,Blue value" else hgroup.long (0xC4+0x80)++0x03 hide.long 0x00 "LTDC_L2CLUTWR,LTDC Layer 2 CLUT Write Register" endif tree.end width 0x0B tree.end endif sif (cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) tree.open "DFSDM (Digital Filter For Sigma Delta Modulators)" tree "DFSDM1" base ad:0x40016000 sif cpuis("STM32F412C*") width 18. tree "Channel 0" if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0C2FGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CH0DATINR register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG0R2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDAT2R,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" if (((per.l(ad:0x40016000+0x0))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x0))&0xC000)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016000+0x0))&0xC000)==0x4000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif else if (((per.l(ad:0x40016000+0x0))&0xC000)==0x00) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016000+0x0))&0xC000)==0x4000) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1C2FGR1,DFSDM Channel Configuration 1 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG1R2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDAT2R,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" if (((per.l(ad:0x40016000+0x20))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x20))&0xC000)==0x00) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016000+0x20))&0xC000)==0x4000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif else if (((per.l(ad:0x40016000+0x20))&0xC000)==0x00) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016000+0x20))&0xC000)==0x4000) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2C2FGR1,DFSDM Channel Configuration 2 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG2R2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDAT2R,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" if (((per.l(ad:0x40016000+0x40))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x40))&0xC000)==0x00) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016000+0x40))&0xC000)==0x4000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif else if (((per.l(ad:0x40016000+0x40))&0xC000)==0x00) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016000+0x40))&0xC000)==0x4000) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif endif tree.end width 19. tree "Module 0 registers" if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" endif textline " " group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F412C*") bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else sif cpuis("STM32F412C*") bitfld.long 0x00 26. " SCDF[2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " else bitfld.long 0x00 27. " SCDF[3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 18. " CKABF[2] ,Channel 2 clock absence flag" "Present,Absent" textline " " else bitfld.long 0x00 19. " CKABF[3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" textline " " endif bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else sif cpuis("STM32F412C*") eventfld.long 0x00 26. " CLRSCDF[2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 27. " CLRSCDF[3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " sif cpuis("STM32F412C*") eventfld.long 0x00 18. " CLRCKABF[2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 19. " CLRCKABF[3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F412C*") bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F412C*") bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif !cpuis("STM32F412C*") eventfld.long 0x00 11. " CLRAWHTF[3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif !cpuis("STM32F412C*") eventfld.long 0x00 3. " CLRAWLTF[3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" endif textline " " group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F412C*") bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F412C*") bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F412C*") bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif !cpuis("STM32F412C*") eventfld.long 0x00 11. " CLRAWHTF[3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif !cpuis("STM32F412C*") eventfld.long 0x00 3. " CLRAWLTF[3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end width 0x0B else width 18. tree "Channel 0" if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0C2FGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CH0DATINR register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG0R2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDAT2R,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" if (((per.l(ad:0x40016000+0x0))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x0))&0xC000)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016000+0x0))&0xC000)==0x4000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif else if (((per.l(ad:0x40016000+0x0))&0xC000)==0x00) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016000+0x0))&0xC000)==0x4000) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1C2FGR1,DFSDM Channel Configuration 1 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG1R2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDAT2R,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" if (((per.l(ad:0x40016000+0x20))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x20))&0xC000)==0x00) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016000+0x20))&0xC000)==0x4000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif else if (((per.l(ad:0x40016000+0x20))&0xC000)==0x00) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016000+0x20))&0xC000)==0x4000) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2C2FGR1,DFSDM Channel Configuration 2 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG2R2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDAT2R,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" if (((per.l(ad:0x40016000+0x40))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x40))&0xC000)==0x00) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016000+0x40))&0xC000)==0x4000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif else if (((per.l(ad:0x40016000+0x40))&0xC000)==0x00) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016000+0x40))&0xC000)==0x4000) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif endif tree.end tree "Channel 3" if (((per.l(ad:0x40016000+0x60))&0x80)==0x0) group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3C2FGR1,DFSDM Channel Configuration 3 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel Configuration 3 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016000+0x60))&0x80)==0x0) group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" else group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG3R2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" endif rgroup.long (0x60+0x0C)++0x03 line.long 0x00 "DFSDM_CH3WDAT2R,DFSDM Channel 3 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 3 watchdog data" if (((per.l(ad:0x40016000+0x60))&0x3000)==0x2000) if (((per.l(ad:0x40016000+0x60))&0xC000)==0x00) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016000+0x60))&0xC000)==0x4000) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif else if (((per.l(ad:0x40016000+0x60))&0xC000)==0x00) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016000+0x60))&0xC000)==0x4000) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif endif tree.end width 19. tree "Module 0 registers" if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" endif textline " " group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F412C*") bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else sif cpuis("STM32F412C*") bitfld.long 0x00 26. " SCDF[2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " else bitfld.long 0x00 27. " SCDF[3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 18. " CKABF[2] ,Channel 2 clock absence flag" "Present,Absent" textline " " else bitfld.long 0x00 19. " CKABF[3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" textline " " endif bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else sif cpuis("STM32F412C*") eventfld.long 0x00 26. " CLRSCDF[2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 27. " CLRSCDF[3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " sif cpuis("STM32F412C*") eventfld.long 0x00 18. " CLRCKABF[2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 19. " CLRCKABF[3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F412C*") bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif if (((per.l(ad:0x40016000+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F412C*") bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif !cpuis("STM32F412C*") eventfld.long 0x00 11. " CLRAWHTF[3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif !cpuis("STM32F412C*") eventfld.long 0x00 3. " CLRAWLTF[3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,?..." textline " " endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO2,TIM3_TRGO2,TIM8_TRGO2,TIM10_OC1,TIM4_TRGO2,TIM6_TRGO1,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" endif textline " " group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F412C*") bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 19. " AWDCH[3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 11. " EXCH[3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F412C*") bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 3. " JCHG[3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif if (((per.l(ad:0x40016000+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F412C*") bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 11. " AWHTF[3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif cpuis("STM32F412C*") bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " else bitfld.long 0x00 3. " AWLTF[3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " endif bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif !cpuis("STM32F412C*") eventfld.long 0x00 11. " CLRAWHTF[3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif !cpuis("STM32F412C*") eventfld.long 0x00 3. " CLRAWLTF[3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " else eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end width 0x0B endif tree.end sif cpuis("STM32F413*")||cpuis("STM32F423?H") tree "DFSDM2" base ad:0x40016400 sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" width 18. tree "Channel 0" if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0C2FGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CH0DATINR register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG0R2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDAT2R,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" if (((per.l(ad:0x40016400+0x0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif else if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1C2FGR1,DFSDM Channel Configuration 1 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG1R2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDAT2R,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" if (((per.l(ad:0x40016400+0x20))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif else if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2C2FGR1,DFSDM Channel Configuration 2 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG2R2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDAT2R,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" if (((per.l(ad:0x40016400+0x40))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif else if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif endif tree.end width 19. tree "Module 0 registers" if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" endif textline " " group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" endif bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 26. " SCDF[2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " CKABF[2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 30. " SCDF[6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " else bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " CKABF[6] ,Channel 6 clock absence flag" "Present,Absent" textline " " else bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" textline " " endif bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" endif textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 26. " CLRSCDF[2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 18. " CLRCKABF[2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 30. " CLRSCDF[6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 22. " CLRCKABF[6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" endif textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" endif textline " " group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 2 registers" if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" else group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" endif textline " " group.long (0x300+0x04)++0x03 line.long 0x00 "DFSDM_FLT2CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x300+0x08)++0x03 line.long 0x00 "DFSDM_FLT2ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x300+0x0C)++0x07 line.long 0x00 "DFSDM_FLT2ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT2JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x300+0x18)++0x03 line.long 0x00 "DFSDM_FLT2JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x300+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT2RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x300+0x20)++0x07 line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x300+0x28)++0x03 line.long 0x00 "DFSDM_FLT2AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x300+0x2C)++0x03 line.long 0x00 "DFSDM_FLT2AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x300+0x30)++0x03 hide.long 0x00 "DFSDM_FLT2EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x300+0x34)++0x03 hide.long 0x00 "DFSDM_FLT2EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x300+0x38)++0x03 line.long 0x00 "DFSDM_FLT2CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 3 registers" if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" endif textline " " group.long (0x400+0x04)++0x03 line.long 0x00 "DFSDM_FLT3CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x400+0x08)++0x03 line.long 0x00 "DFSDM_FLT3ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x400+0x0C)++0x07 line.long 0x00 "DFSDM_FLT3ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT3JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x400+0x18)++0x03 line.long 0x00 "DFSDM_FLT3JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x400+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT3RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x400+0x20)++0x07 line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x400+0x28)++0x03 line.long 0x00 "DFSDM_FLT3AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x400+0x2C)++0x03 line.long 0x00 "DFSDM_FLT3AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x400+0x30)++0x03 hide.long 0x00 "DFSDM_FLT3EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x400+0x34)++0x03 hide.long 0x00 "DFSDM_FLT3EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x400+0x38)++0x03 line.long 0x00 "DFSDM_FLT3CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end width 0x0B elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" width 18. tree "Channel 0" if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0C2FGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CH0DATINR register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG0R2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDAT2R,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" if (((per.l(ad:0x40016400+0x0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif else if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1C2FGR1,DFSDM Channel Configuration 1 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG1R2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDAT2R,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" if (((per.l(ad:0x40016400+0x20))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif else if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2C2FGR1,DFSDM Channel Configuration 2 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG2R2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDAT2R,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" if (((per.l(ad:0x40016400+0x40))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif else if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif endif tree.end tree "Channel 3" if (((per.l(ad:0x40016400+0x60))&0x80)==0x0) group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3C2FGR1,DFSDM Channel Configuration 3 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel Configuration 3 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x60))&0x80)==0x0) group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" else group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG3R2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" endif rgroup.long (0x60+0x0C)++0x03 line.long 0x00 "DFSDM_CH3WDAT2R,DFSDM Channel 3 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 3 watchdog data" if (((per.l(ad:0x40016400+0x60))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x60))&0xC000)==0x00) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016400+0x60))&0xC000)==0x4000) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif else if (((per.l(ad:0x40016400+0x60))&0xC000)==0x00) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016400+0x60))&0xC000)==0x4000) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif endif tree.end tree "Channel 4" if (((per.l(ad:0x40016400+0x80))&0x80)==0x0) group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4C2FGR1,DFSDM Channel Configuration 4 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CH4DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel Configuration 4 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CH4DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x80))&0x80)==0x0) group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CH4CFGR2,DFSDM Channel Configuration 4 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" else group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG4R2,DFSDM Channel Configuration 4 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" endif rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DFSDM_CH4WDAT2R,DFSDM Channel 4 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 4 watchdog data" if (((per.l(ad:0x40016400+0x80))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x80))&0xC000)==0x00) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" elif (((per.l(ad:0x40016400+0x80))&0xC000)==0x4000) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4" else group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4" endif else if (((per.l(ad:0x40016400+0x80))&0xC000)==0x00) rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" elif (((per.l(ad:0x40016400+0x80))&0xC000)==0x4000) rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4" else rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4" endif endif tree.end tree "Channel 5" if (((per.l(ad:0x40016400+0xA0))&0x80)==0x0) group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5C2FGR1,DFSDM Channel Configuration 5 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CH5DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel Configuration 5 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CH5DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0xA0))&0x80)==0x0) group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CH5CFGR2,DFSDM Channel Configuration 5 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" else group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG5R2,DFSDM Channel Configuration 5 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" endif rgroup.long (0xA0+0x0C)++0x03 line.long 0x00 "DFSDM_CH5WDAT2R,DFSDM Channel 5 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 5 watchdog data" if (((per.l(ad:0x40016400+0xA0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0xA0))&0xC000)==0x00) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" elif (((per.l(ad:0x40016400+0xA0))&0xC000)==0x4000) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5" else group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 5+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5" endif else if (((per.l(ad:0x40016400+0xA0))&0xC000)==0x00) rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" elif (((per.l(ad:0x40016400+0xA0))&0xC000)==0x4000) rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5" else rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 5+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5" endif endif tree.end tree "Channel 6" if (((per.l(ad:0x40016400+0xC0))&0x80)==0x0) group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6C2FGR1,DFSDM Channel Configuration 6 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CH6DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel Configuration 6 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CH6DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0xC0))&0x80)==0x0) group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CH6CFGR2,DFSDM Channel Configuration 6 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" else group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG6R2,DFSDM Channel Configuration 6 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" endif rgroup.long (0xC0+0x0C)++0x03 line.long 0x00 "DFSDM_CH6WDAT2R,DFSDM Channel 6 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 6 watchdog data" if (((per.l(ad:0x40016400+0xC0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0xC0))&0xC000)==0x00) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" elif (((per.l(ad:0x40016400+0xC0))&0xC000)==0x4000) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6" else group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6" endif else if (((per.l(ad:0x40016400+0xC0))&0xC000)==0x00) rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" elif (((per.l(ad:0x40016400+0xC0))&0xC000)==0x4000) rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6" else rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6" endif endif tree.end width 19. tree "Module 0 registers" if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" endif textline " " group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" endif bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 26. " SCDF[2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " CKABF[2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 30. " SCDF[6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " else bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " CKABF[6] ,Channel 6 clock absence flag" "Present,Absent" textline " " else bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" textline " " endif bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" endif textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 26. " CLRSCDF[2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 18. " CLRCKABF[2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 30. " CLRSCDF[6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 22. " CLRCKABF[6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" endif textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" endif textline " " group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 2 registers" if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" else group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" endif textline " " group.long (0x300+0x04)++0x03 line.long 0x00 "DFSDM_FLT2CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x300+0x08)++0x03 line.long 0x00 "DFSDM_FLT2ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x300+0x0C)++0x07 line.long 0x00 "DFSDM_FLT2ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT2JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x300+0x18)++0x03 line.long 0x00 "DFSDM_FLT2JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x300+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT2RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x300+0x20)++0x07 line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x300+0x28)++0x03 line.long 0x00 "DFSDM_FLT2AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x300+0x2C)++0x03 line.long 0x00 "DFSDM_FLT2AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x300+0x30)++0x03 hide.long 0x00 "DFSDM_FLT2EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x300+0x34)++0x03 hide.long 0x00 "DFSDM_FLT2EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x300+0x38)++0x03 line.long 0x00 "DFSDM_FLT2CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 3 registers" if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" endif textline " " group.long (0x400+0x04)++0x03 line.long 0x00 "DFSDM_FLT3CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x400+0x08)++0x03 line.long 0x00 "DFSDM_FLT3ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x400+0x0C)++0x07 line.long 0x00 "DFSDM_FLT3ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT3JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x400+0x18)++0x03 line.long 0x00 "DFSDM_FLT3JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x400+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT3RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x400+0x20)++0x07 line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x400+0x28)++0x03 line.long 0x00 "DFSDM_FLT3AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x400+0x2C)++0x03 line.long 0x00 "DFSDM_FLT3AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x400+0x30)++0x03 hide.long 0x00 "DFSDM_FLT3EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x400+0x34)++0x03 hide.long 0x00 "DFSDM_FLT3EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x400+0x38)++0x03 line.long 0x00 "DFSDM_FLT3CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end width 0x0B else width 18. tree "Channel 0" if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0C2FGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CH0DATINR register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x0++0x3 line.long 0x00 "DFSDM_CH0CFGR1,DFSDM Channel Configuration 0 Register" bitfld.long 0x00 31. " DFSDMEN ,Global enable for DFSDM interface" "Disabled,Enabled" bitfld.long 0x00 30. " CKOUTSRC ,Output serial clock source selection" "SysClock,AudioClock" hexmask.long.byte 0x00 16.--23. 1. " CKOUTDIV ,Output serial clock divider" textline " " rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN0R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 0" "Ext serial inputs,,Internal DFSDM_CH0DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(0+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 0" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 0" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 0" "Ext DFSDM_CKIN0(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 0" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x0))&0x80)==0x0) group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CH0CFGR2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" else group.long (0x0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG0R2,DFSDM Channel Configuration 0 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 0" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH0AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 0" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 0" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 0" endif rgroup.long (0x0+0x0C)++0x03 line.long 0x00 "DFSDM_CH0WDAT2R,DFSDM Channel 0 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 0 watchdog data" if (((per.l(ad:0x40016400+0x0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else group.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif else if (((per.l(ad:0x40016400+0x0))&0xC000)==0x00) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 0" elif (((per.l(ad:0x40016400+0x0))&0xC000)==0x4000) rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 0" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 0" else rgroup.long (0x0+0x10)++0x03 line.long 0x00 "DFSDM_CH0DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 0+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 0" endif endif tree.end tree "Channel 1" if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1C2FGR1,DFSDM Channel Configuration 1 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x20++0x3 line.long 0x00 "DFSDM_CH1CFGR1,DFSDM Channel Configuration 1 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN1R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 1" "Ext serial inputs,,Internal DFSDM_CH1DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(1+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 1" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 1" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 1" "Ext DFSDM_CKIN1(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 1" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x20))&0x80)==0x0) group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CH1CFGR2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" else group.long (0x20+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG1R2,DFSDM Channel Configuration 1 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 1" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH1AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 1" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 1" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 1" endif rgroup.long (0x20+0x0C)++0x03 line.long 0x00 "DFSDM_CH1WDAT2R,DFSDM Channel 1 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 1 watchdog data" if (((per.l(ad:0x40016400+0x20))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else group.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif else if (((per.l(ad:0x40016400+0x20))&0xC000)==0x00) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 1" elif (((per.l(ad:0x40016400+0x20))&0xC000)==0x4000) rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 1" else rgroup.long (0x20+0x10)++0x03 line.long 0x00 "DFSDM_CH1DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 1+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 1" endif endif tree.end tree "Channel 2" if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2C2FGR1,DFSDM Channel Configuration 2 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x40++0x3 line.long 0x00 "DFSDM_CH2CFGR1,DFSDM Channel Configuration 2 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN2R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 2" "Ext serial inputs,,Internal DFSDM_CH2DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(2+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 2" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 2" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 2" "Ext DFSDM_CKIN2(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 2" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x40))&0x80)==0x0) group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CH2CFGR2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" else group.long (0x40+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG2R2,DFSDM Channel Configuration 2 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 2" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH2AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 2" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 2" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 2" endif rgroup.long (0x40+0x0C)++0x03 line.long 0x00 "DFSDM_CH2WDAT2R,DFSDM Channel 2 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 2 watchdog data" if (((per.l(ad:0x40016400+0x40))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else group.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif else if (((per.l(ad:0x40016400+0x40))&0xC000)==0x00) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 2" elif (((per.l(ad:0x40016400+0x40))&0xC000)==0x4000) rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 2" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 2" else rgroup.long (0x40+0x10)++0x03 line.long 0x00 "DFSDM_CH2DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 2+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 2" endif endif tree.end tree "Channel 3" if (((per.l(ad:0x40016400+0x60))&0x80)==0x0) group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3C2FGR1,DFSDM Channel Configuration 3 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x60++0x3 line.long 0x00 "DFSDM_CH3CFGR1,DFSDM Channel Configuration 3 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN3R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 3" "Ext serial inputs,,Internal DFSDM_CH3DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(3+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 3" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 3" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 3" "Ext DFSDM_CKIN3(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 3" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x60))&0x80)==0x0) group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CH3CFGR2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" else group.long (0x60+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG3R2,DFSDM Channel Configuration 3 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 3" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH3AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 3" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 3" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 3" endif rgroup.long (0x60+0x0C)++0x03 line.long 0x00 "DFSDM_CH3WDAT2R,DFSDM Channel 3 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 3 watchdog data" if (((per.l(ad:0x40016400+0x60))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x60))&0xC000)==0x00) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016400+0x60))&0xC000)==0x4000) group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else group.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif else if (((per.l(ad:0x40016400+0x60))&0xC000)==0x00) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 3" elif (((per.l(ad:0x40016400+0x60))&0xC000)==0x4000) rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 3" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 3" else rgroup.long (0x60+0x10)++0x03 line.long 0x00 "DFSDM_CH3DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 3+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 3" endif endif tree.end tree "Channel 4" if (((per.l(ad:0x40016400+0x80))&0x80)==0x0) group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4C2FGR1,DFSDM Channel Configuration 4 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CH4DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0x80++0x3 line.long 0x00 "DFSDM_CH4CFGR1,DFSDM Channel Configuration 4 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN4R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 4" "Ext serial inputs,,Internal DFSDM_CH4DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(4+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 4" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 4" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 4" "Ext DFSDM_CKIN4(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 4" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0x80))&0x80)==0x0) group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CH4CFGR2,DFSDM Channel Configuration 4 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" else group.long (0x80+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG4R2,DFSDM Channel Configuration 4 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 4" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH4AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 4" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 4" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 4" endif rgroup.long (0x80+0x0C)++0x03 line.long 0x00 "DFSDM_CH4WDAT2R,DFSDM Channel 4 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 4 watchdog data" if (((per.l(ad:0x40016400+0x80))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0x80))&0xC000)==0x00) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" elif (((per.l(ad:0x40016400+0x80))&0xC000)==0x4000) group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4" else group.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4" endif else if (((per.l(ad:0x40016400+0x80))&0xC000)==0x00) rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 4" elif (((per.l(ad:0x40016400+0x80))&0xC000)==0x4000) rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 4" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 4" else rgroup.long (0x80+0x10)++0x03 line.long 0x00 "DFSDM_CH4DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 4+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 4" endif endif tree.end tree "Channel 5" if (((per.l(ad:0x40016400+0xA0))&0x80)==0x0) group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5C2FGR1,DFSDM Channel Configuration 5 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CH5DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0xA0++0x3 line.long 0x00 "DFSDM_CH5CFGR1,DFSDM Channel Configuration 5 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN5R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 5" "Ext serial inputs,,Internal DFSDM_CH5DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(5+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 5" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 5" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 5" "Ext DFSDM_CKIN5(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 5" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0xA0))&0x80)==0x0) group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CH5CFGR2,DFSDM Channel Configuration 5 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" else group.long (0xA0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG5R2,DFSDM Channel Configuration 5 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 5" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH5AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 5" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 5" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 5" endif rgroup.long (0xA0+0x0C)++0x03 line.long 0x00 "DFSDM_CH5WDAT2R,DFSDM Channel 5 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 5 watchdog data" if (((per.l(ad:0x40016400+0xA0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0xA0))&0xC000)==0x00) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" elif (((per.l(ad:0x40016400+0xA0))&0xC000)==0x4000) group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5" else group.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 5+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5" endif else if (((per.l(ad:0x40016400+0xA0))&0xC000)==0x00) rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 5" elif (((per.l(ad:0x40016400+0xA0))&0xC000)==0x4000) rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 5" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 5" else rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "DFSDM_CH5DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 5+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 5" endif endif tree.end tree "Channel 6" if (((per.l(ad:0x40016400+0xC0))&0x80)==0x0) group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6C2FGR1,DFSDM Channel Configuration 6 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CH6DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0xC0++0x3 line.long 0x00 "DFSDM_CH6CFGR1,DFSDM Channel Configuration 6 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN6R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 6" "Ext serial inputs,,Internal DFSDM_CH6DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(6+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 6" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 6" "Ext DFSDM_CKIN6(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 6" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0xC0))&0x80)==0x0) group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CH6CFGR2,DFSDM Channel Configuration 6 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" else group.long (0xC0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG6R2,DFSDM Channel Configuration 6 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 6" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH6AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 6" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 6" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 6" endif rgroup.long (0xC0+0x0C)++0x03 line.long 0x00 "DFSDM_CH6WDAT2R,DFSDM Channel 6 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 6 watchdog data" if (((per.l(ad:0x40016400+0xC0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0xC0))&0xC000)==0x00) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" elif (((per.l(ad:0x40016400+0xC0))&0xC000)==0x4000) group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6" else group.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6" endif else if (((per.l(ad:0x40016400+0xC0))&0xC000)==0x00) rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 6" elif (((per.l(ad:0x40016400+0xC0))&0xC000)==0x4000) rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 6" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 6" else rgroup.long (0xC0+0x10)++0x03 line.long 0x00 "DFSDM_CH6DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 6+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 6" endif endif tree.end tree "Channel 7" if (((per.l(ad:0x40016400+0xE0))&0x80)==0x0) group.long 0xE0++0x3 line.long 0x00 "DFSDM_CH7C2FGR1,DFSDM Channel Configuration 7 Register" bitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,?..." bitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CH7DATINR,?..." bitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" bitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " else group.long 0xE0++0x3 line.long 0x00 "DFSDM_CH7CFGR1,DFSDM Channel Configuration 7 Register" rbitfld.long 0x00 14.--15. " DATPACK ,Data packing mode in DFSDM_CHDATIN7R register" "Standard,Interleaved,Dual,?..." rbitfld.long 0x00 12.--13. " DATMPX ,Input data multiplexer for channel 7" "Ext serial inputs,,Internal DFSDM_CH7DATINR,?..." rbitfld.long 0x00 8. " CHINSEL ,Channel inputs selection" "This channel,(7+1) mod 8 channel" textline " " bitfld.long 0x00 7. " CHEN ,Channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " CKABEN ,Clock absence detector enable on channel 7" "Disabled,Enabled" bitfld.long 0x00 5. " SCDEN ,Short-circuit detector enable on channel 7" "Disabled,Enabled" textline " " rbitfld.long 0x00 2.--3. " SPICKSEL ,SPI clock select for channel 7" "Ext DFSDM_CKIN7(SITP),Int DFSDM_CKOUT(SITP),Int DFSDM_CKOUT(Falling),Int DFSDM_CKOUT(Rising)" rbitfld.long 0x00 0.--1. " SITP ,Serial interface type for channel 7" "SPI(Rising),SPI(Falling),Manchester(Rising0Falling1),Manchester(Rising1Falling0)" textline " " endif if (((per.l(ad:0x40016400+0xE0))&0x80)==0x0) group.long (0xE0+0x04)++0x07 line.long 0x00 "DFSDM_CH7CFGR2,DFSDM Channel Configuration 7 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7" bitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" bitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3" bitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7" else group.long (0xE0+0x04)++0x07 line.long 0x00 "DFSDM_CHCFG7R2,DFSDM Channel Configuration 7 Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,24-bit calibration offset for channel 7" rbitfld.long 0x00 3.--7. " DTRBS ,Data right bit-shift for channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DFSDM_CH7AWSCDR,DFSDM Analog Watchdog And Short-circuit Detector Register" rbitfld.long 0x04 22.--23. " AWFORD ,Analog watchdog Sinc filter order on channel 7" "FastSinc,Sinc1,Sinc2,Sinc3" rbitfld.long 0x04 16.--20. " AWFOSR ,Analog watchdog filter oversampling ratio (decimation rate) on channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 15. " BKSCD3 ,Break 3 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " bitfld.long 0x04 14. " BKSCD2 ,Break 2 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 13. " BKSCD1 ,Break 1 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" bitfld.long 0x04 12. " BKSCD0 ,Break 0 signal assignment for short-circuit detector on channel 7" "Not assigned,Assigned" textline " " hexmask.long.byte 0x04 0.--7. 1. " SCDT ,Short-circuit detector threshold for channel 7" endif rgroup.long (0xE0+0x0C)++0x03 line.long 0x00 "DFSDM_CH7WDAT2R,DFSDM Channel 7 Watchdog Filter Data Register" hexmask.long.word 0x00 0.--15. 1. " WDATA ,Input channel 7 watchdog data" if (((per.l(ad:0x40016400+0xE0))&0x3000)==0x2000) if (((per.l(ad:0x40016400+0xE0))&0xC000)==0x00) group.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" elif (((per.l(ad:0x40016400+0xE0))&0xC000)==0x4000) group.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 7" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 7" else group.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 7+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 7" endif else if (((per.l(ad:0x40016400+0xE0))&0xC000)==0x00) rgroup.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Input data for channel 7" elif (((per.l(ad:0x40016400+0xE0))&0xC000)==0x4000) rgroup.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Second sample of input data for channel 7" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,First sample of input data for channel 7" else rgroup.long (0xE0+0x10)++0x03 line.long 0x00 "DFSDM_CH7DATINR,DFSDM Channel Data Input Register" hexmask.long.word 0x00 16.--31. 1. " INDAT1 ,Sample of input data for channel 7+1" hexmask.long.word 0x00 0.--15. 1. " INDAT0 ,Sample of input data for channel 7" endif endif tree.end width 19. tree "Module 0 registers" if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" else group.long 0x100++0x03 line.long 0x00 "DFSDM_FLT0CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT0 enable" "Disabled,Enabled" endif textline " " group.long (0x100+0x04)++0x03 line.long 0x00 "DFSDM_FLT0CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 18. " AWDCH[2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " EXCH[2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CKABIE ,Clock absence interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCDIE ,Short-circuit detector interrupt enable" "Disabled,Enabled" endif bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x100+0x08)++0x03 line.long 0x00 "DFSDM_FLT0ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 26. " SCDF[2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 18. " CKABF[2] ,Channel 2 clock absence flag" "Present,Absent" bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 30. " SCDF[6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " else bitfld.long 0x00 31. " SCDF[7] ,Channel 7 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag" "Not occurred,Occurred" bitfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag" "Not occurred,Occurred" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " CKABF[6] ,Channel 6 clock absence flag" "Present,Absent" textline " " else bitfld.long 0x00 23. " CKABF[7] ,Channel 7 clock absence flag" "Present,Absent" bitfld.long 0x00 22. " [6] ,Channel 6 clock absence flag" "Present,Absent" textline " " endif bitfld.long 0x00 21. " [5] ,Channel 5 clock absence flag" "Present,Absent" bitfld.long 0x00 20. " [4] ,Channel 4 clock absence flag" "Present,Absent" bitfld.long 0x00 19. " [3] ,Channel 3 clock absence flag" "Present,Absent" bitfld.long 0x00 18. " [2] ,Channel 2 clock absence flag" "Present,Absent" textline " " bitfld.long 0x00 17. " [1] ,Channel 1 clock absence flag" "Present,Absent" bitfld.long 0x00 16. " [0] ,Channel 0 clock absence flag" "Present,Absent" endif textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x100+0x0C)++0x07 line.long 0x00 "DFSDM_FLT0ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 26. " CLRSCDF[2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit 0 detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 18. " CLRCKABF[2] ,Channel 2 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 30. " CLRSCDF[6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 31. " CLRSCDF[7] ,Channel 7 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 30. " [6] ,Channel 6 short-circuit detector flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 29. " [5] ,Channel 5 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 28. " [4] ,Channel 4 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 27. " [3] ,Channel 3 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 26. " [2] ,Channel 2 short-circuit detector flag clear" "No effect,Clear" textline " " eventfld.long 0x00 25. " [1] ,Channel 1 short-circuit detector flag clear" "No effect,Clear" eventfld.long 0x00 24. " [0] ,Channel 0 short-circuit detector flag clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 22. " CLRCKABF[6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " else eventfld.long 0x00 23. " CLRCKABF[7] ,Channel 7 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 22. " [6] ,Channel 6 clock absence flag clear" "No effect,Clear" textline " " endif eventfld.long 0x00 21. " [5] ,Channel 5 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 20. " [4] ,Channel 4 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 19. " [3] ,Channel 3 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 18. " [2] ,Channel 2 clock absence flag clear" "No effect,Clear" textline " " eventfld.long 0x00 17. " [1] ,Channel 1 clock absence flag clear" "No effect,Clear" eventfld.long 0x00 16. " [0] ,Channel 0 clock absence flag clear" "No effect,Clear" endif textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT0JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x100))&0x1)==0x0) group.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x100+0x14)++0x03 line.long 0x00 "DFSDM_FLT0FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x100+0x18)++0x03 line.long 0x00 "DFSDM_FLT0JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x100+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT0RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x100+0x20)++0x07 line.long 0x00 "DFSDM_FLT0AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT0AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x100+0x28)++0x03 line.long 0x00 "DFSDM_FLT0AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x100+0x2C)++0x03 line.long 0x00 "DFSDM_FLT0AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "DFSDM_FLT0EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x100+0x34)++0x03 hide.long 0x00 "DFSDM_FLT0EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x100+0x38)++0x03 line.long 0x00 "DFSDM_FLT0CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 1 registers" if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "DFSDM_FLT1CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM6_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT1 enable" "Disabled,Enabled" endif textline " " group.long (0x200+0x04)++0x03 line.long 0x00 "DFSDM_FLT1CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x200+0x08)++0x03 line.long 0x00 "DFSDM_FLT1ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x200+0x0C)++0x07 line.long 0x00 "DFSDM_FLT1ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT1JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x200))&0x1)==0x0) group.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x200+0x14)++0x03 line.long 0x00 "DFSDM_FLT1FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x200+0x18)++0x03 line.long 0x00 "DFSDM_FLT1JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x200+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT1RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x200+0x20)++0x07 line.long 0x00 "DFSDM_FLT1AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT1AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x200+0x28)++0x03 line.long 0x00 "DFSDM_FLT1AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x200+0x2C)++0x03 line.long 0x00 "DFSDM_FLT1AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x200+0x30)++0x03 hide.long 0x00 "DFSDM_FLT1EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x200+0x34)++0x03 hide.long 0x00 "DFSDM_FLT1EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x200+0x38)++0x03 line.long 0x00 "DFSDM_FLT1CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 2 registers" if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" else group.long 0x300++0x03 line.long 0x00 "DFSDM_FLT2CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM10_OC1,TIM4_TRGO4,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT2 enable" "Disabled,Enabled" endif textline " " group.long (0x300+0x04)++0x03 line.long 0x00 "DFSDM_FLT2CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x300+0x08)++0x03 line.long 0x00 "DFSDM_FLT2ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x300+0x0C)++0x07 line.long 0x00 "DFSDM_FLT2ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT2JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x300))&0x1)==0x0) group.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x300+0x14)++0x03 line.long 0x00 "DFSDM_FLT2FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x300+0x18)++0x03 line.long 0x00 "DFSDM_FLT2JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x300+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT2RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x300+0x20)++0x07 line.long 0x00 "DFSDM_FLT2AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT2AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x300+0x28)++0x03 line.long 0x00 "DFSDM_FLT2AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x300+0x2C)++0x03 line.long 0x00 "DFSDM_FLT2AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x300+0x30)++0x03 hide.long 0x00 "DFSDM_FLT2EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x300+0x34)++0x03 hide.long 0x00 "DFSDM_FLT2EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x300+0x38)++0x03 line.long 0x00 "DFSDM_FLT2CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end tree "Module 3 registers" if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif bitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" bitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " bitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" textline " " endif bitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" bitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "DFSDM_FLT3CR1,DFSDM Control Register 1" bitfld.long 0x00 30. " AWFSEL ,Analog watchdog fast mode select" "Data output value,Chan transceivers value" bitfld.long 0x00 29. " FAST ,Fast conversion mode selection for regular conversions" "Disabled,Enabled" textline " " sif cpuis("STM32F412*") bitfld.long 0x00 24.--25. " RCH ,Regular channel selection" "CH0,CH1,?..." textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,?..." textline " " elif cpuis("STM32F413R*")||cpu()=="STM32F423RH" bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,?..." textline " " else bitfld.long 0x00 24.--26. " RCH ,Regular channel selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7" textline " " endif endif rbitfld.long 0x00 21. " RDMAEN ,DMA channel enabled to read data for the regular conversion" "Disabled,Enabled" rbitfld.long 0x00 19. " RSYNC ,Launch regular conversion synchronously with DFSDM_FLT0" "Not launched,Launched" bitfld.long 0x00 18. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeatedly" bitfld.long 0x00 17. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Conversion started" textline " " rbitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising edge,Falling edge,Both edges" textline " " sif cpuis("STM32F412*") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM3_TRGO,TIM8_TRGO,TIM10_OC1,TIM4_TRGO,TIM6_TRGO,EXTI11,EXTI15" textline " " elif (cpuis("STM32H743*")||cpuis("STM32H753*")) rbitfld.long 0x00 8.--12. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO,TIM1_TRGO2,TIM8_TRGO,TIM8_TRGO2,TIM3_TRGO,TIM4_TRGO,TIM16_OC1,TIM6_TRGO,TIM7_TRGO,HRTIM1_ADCTRG1,HRTIM1_ADCTRG3,,EXTI11,EXTI15,LPTIMER1,LPTIMER2,LPTIMER3,?..." textline " " elif cpuis("STM32F413*")||cpuis("STM32F423?H") rbitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM1_TRGO3,TIM3_TRGO3,TIM8_TRGO4,TIM2_TRGO2,TIM11_OC1,TIM7_TRGO2,EXTI11,EXTI15" textline " " endif rbitfld.long 0x00 5. " JDMAEN ,DMA channel enable to read data for the injected channel group" "Disabled,Enabled" rbitfld.long 0x00 4. " JSCAN ,Scanning conversion mode for injected conversions" "One conv,Series of conv" rbitfld.long 0x00 3. " JSYNC ,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "Not launched,Launched" bitfld.long 0x00 1. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Start" textline " " bitfld.long 0x00 0. " DFEN ,DFSDM_FLT3 enable" "Disabled,Enabled" endif textline " " group.long (0x400+0x04)++0x03 line.long 0x00 "DFSDM_FLT3CR2,DFSDM Control Register 2" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 22. " AWDCH[6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 23. " AWDCH[7] ,Analog watchdog channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Analog watchdog channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 21. " [5] ,Analog watchdog channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Analog watchdog channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Analog watchdog channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Analog watchdog channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " [1] ,Analog watchdog channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Analog watchdog channel 0 selection" "Disabled,Enabled" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " EXCH[6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " else bitfld.long 0x00 15. " EXCH[7] ,Extremes detector channel 7 selection" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Extremes detector channel 6 selection" "Disabled,Enabled" textline " " endif bitfld.long 0x00 13. " [5] ,Extremes detector channel 5 selection" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Extremes detector channel 4 selection" "Disabled,Enabled" bitfld.long 0x00 11. " [3] ,Extremes detector channel 3 selection" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Extremes detector channel 2 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " [1] ,Extremes detector channel 1 selection" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Extremes detector channel 0 selection" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " JOVRIE ,Injected data overrunt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled" endif textline " " rgroup.long (0x400+0x08)++0x03 line.long 0x00 "DFSDM_FLT3ISR,DFSDM Interrupt And Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" else textline " " bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "No request,In progress" bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "No request,In progress" bitfld.long 0x00 4. " AWDF ,Analog watchdog" "Not occurred,Occurred" bitfld.long 0x00 3. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not occurred,Occurred" bitfld.long 0x00 1. " REOCF ,End of regular conversion flag" "Not completed,Completed" bitfld.long 0x00 0. " JEOCF ,End of injected conversion flag" "Not completed,Completed" endif textline " " group.long (0x400+0x0C)++0x07 line.long 0x00 "DFSDM_FLT3ICR,DFSDM Interrupt Flag Clear Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" else textline " " eventfld.long 0x00 3. " CLRROVRF ,Regular conversion overrun flag clear" "No effect,Clear" eventfld.long 0x00 2. " CLRJOVRF ,Injected conversion overrun flag clear" "No effect,Clear" endif line.long 0x04 "DFSDM_FLT3JCHGR,DFSDM Injected Channel Group Selection Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" textline " " bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x04 2. " JCHG[2] ,Injected channel 2 group selection" "Excluded,Included" bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x04 6. " JCHG[6] ,Injected channel 6 group selection" "Excluded,Included" textline " " else bitfld.long 0x04 7. " JCHG[7] ,Injected channel 7 group selection" "Excluded,Included" bitfld.long 0x04 6. " [6] ,Injected channel 6 group selection" "Excluded,Included" textline " " endif bitfld.long 0x04 5. " [5] ,Injected channel 5 group selection" "Excluded,Included" bitfld.long 0x04 4. " [4] ,Injected channel 4 group selection" "Excluded,Included" bitfld.long 0x04 3. " [3] ,Injected channel 3 group selection" "Excluded,Included" bitfld.long 0x04 2. " [2] ,Injected channel 2 group selection" "Excluded,Included" textline " " bitfld.long 0x04 1. " [1] ,Injected channel 1 group selection" "Excluded,Included" bitfld.long 0x04 0. " [0] ,Injected channel 0 group selection" "Excluded,Included" endif endif if (((per.l(ad:0x40016400+0x400))&0x1)==0x0) group.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" else rgroup.long (0x400+0x14)++0x03 line.long 0x00 "DFSDM_FLT3FCR,DFSDM Filter Control Register" bitfld.long 0x00 29.--31. " FORD ,Sinc filter order" "FastSinc,Sinc1,Sinc2,Sinc3,Sinc4,Sinc5,?..." hexmask.long.word 0x00 16.--25. 1. " FOSR ,Sinc filter oversampling ratio (decimation rate)" hexmask.long.byte 0x00 0.--7. 1. " IOSR ,Integrator oversampling ratio (averaging length)" endif rgroup.long (0x400+0x18)++0x03 line.long 0x00 "DFSDM_FLT3JDATAR,Injected Group Conversion Data" hexmask.long.tbyte 0x00 8.--31. 1. " JDATA ,Injected group conversion data" bitfld.long 0x00 0.--2. " JDATACH ,Injected channel most recently converted" "0,1,2,3,4,5,6,7" hgroup.long (0x400+0x1C)++0x03 hide.long 0x00 "DFSDM_FLT3RDATAR,DFSDM Data Register For The Regular Channel" in textline " " group.long (0x400+0x20)++0x07 line.long 0x00 "DFSDM_FLT3AWHTR,DFSDM Analog Watchdog High Threshold Register" hexmask.long.tbyte 0x00 8.--31. 1. " AWHT ,Analog watchdog high threshold" textline " " bitfld.long 0x00 3. " BKAWH[3] ,Break signal 3 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 2. " [2] ,Break signal 2 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 1. " [1] ,Break signal 1 assignment to analog watchdog high threshold event" "Not assigned,Assigned" bitfld.long 0x00 0. " [0] ,Break signal 0 assignment to analog watchdog high threshold event" "Not assigned,Assigned" line.long 0x04 "DFSDM_FLT3AWLTR,DFSDM Analog Watchdog Low Threshold Register" hexmask.long.tbyte 0x04 8.--31. 1. " AWLT ,Analog watchdog low threshold" textline " " bitfld.long 0x04 3. " BKAWL[3] ,Break signal 3 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 2. " [2] ,Break signal 2 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 1. " [1] ,Break signal 1 assignment to analog watchdog low threshold event" "Not assigned,Assigned" bitfld.long 0x04 0. " [0] ,Break signal 0 assignment to analog watchdog low threshold event" "Not assigned,Assigned" textline " " rgroup.long (0x400+0x28)++0x03 line.long 0x00 "DFSDM_FLT3AWSR,DFSDM Analog Watchdog Status Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" textline " " bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" bitfld.long 0x00 10. " AWHTF[2] ,Analog watchdog high threshold flag 2" "No error,Error" bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " bitfld.long 0x00 2. " AWLTF[2] ,Analog watchdog low threshold flag 2" "No error,Error" bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" textline " " else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") bitfld.long 0x00 14. " AWHTF[6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 15. " AWHTF[7] ,Analog watchdog high threshold flag 7" "No error,Error" bitfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5" "No error,Error" bitfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4" "No error,Error" bitfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3" "No error,Error" bitfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1" "No error,Error" bitfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0" "No error,Error" textline " " sif !cpuis("STM32F413R*")&&!(cpu()=="STM32F423RH") bitfld.long 0x00 7. " AWLTF[7] ,Analog watchdog low threshold flag 7" "No error,Error" bitfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " else bitfld.long 0x00 6. " AWLTF[6] ,Analog watchdog low threshold flag 6" "No error,Error" textline " " endif bitfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5" "No error,Error" bitfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4" "No error,Error" bitfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3" "No error,Error" bitfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2" "No error,Error" textline " " bitfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1" "No error,Error" bitfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0" "No error,Error" endif endif group.long (0x400+0x2C)++0x03 line.long 0x00 "DFSDM_FLT3AWCFR,DFSDM Analog Watchdog Clear Flag Register" sif (cpuis("STM32H743*")||cpuis("STM32H753*")) eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" textline " " eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413C*")||cpu()=="STM32F423CH" eventfld.long 0x00 10. " CLRAWHTF[2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " eventfld.long 0x00 2. " CLRAWLTF[2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" else sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 14. " CLRAWHTF[6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 15. " CLRAWHTF[7] ,Analog watchdog high threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 14. " [6] ,Analog watchdog high threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 13. " [5] ,Analog watchdog high threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 12. " [4] ,Analog watchdog high threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 11. " [3] ,Analog watchdog high threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 10. " [2] ,Analog watchdog high threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 9. " [1] ,Analog watchdog high threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 8. " [0] ,Analog watchdog high threshold flag 0 clear" "No effect,Clear" textline " " sif cpuis("STM32F413R*")||(cpu()=="STM32F423RH") eventfld.long 0x00 6. " CLRAWLTF[6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " else eventfld.long 0x00 7. " CLRAWLTF[7] ,Analog watchdog low threshold flag 7 clear" "No effect,Clear" eventfld.long 0x00 6. " [6] ,Analog watchdog low threshold flag 6 clear" "No effect,Clear" textline " " endif eventfld.long 0x00 5. " [5] ,Analog watchdog low threshold flag 5 clear" "No effect,Clear" eventfld.long 0x00 4. " [4] ,Analog watchdog low threshold flag 4 clear" "No effect,Clear" eventfld.long 0x00 3. " [3] ,Analog watchdog low threshold flag 3 clear" "No effect,Clear" eventfld.long 0x00 2. " [2] ,Analog watchdog low threshold flag 2 clear" "No effect,Clear" textline " " eventfld.long 0x00 1. " [1] ,Analog watchdog low threshold flag 1 clear" "No effect,Clear" eventfld.long 0x00 0. " [0] ,Analog watchdog low threshold flag 0 clear" "No effect,Clear" endif endif hgroup.long (0x400+0x30)++0x03 hide.long 0x00 "DFSDM_FLT3EXMAX,DFSDM Extremes Detector Maximum Register" in hgroup.long (0x400+0x34)++0x03 hide.long 0x00 "DFSDM_FLT3EXMIN,DFSDM Extremes Detector Minimum Register" in rgroup.long (0x400+0x38)++0x03 line.long 0x00 "DFSDM_FLT3CNVTIMR,DFSDM Conversion Timer Register" hexmask.long 0x00 4.--31. 1. " CNVCNT ,28-bit timer counting conversion time t = CNVCNT / fDFSDM_CKIN" tree.end width 0x0B endif tree.end endif tree.end endif sif cpuis("STM32F469*")||cpuis("STM32F479*") tree "DSIHOST (Display Serial Interface)" base ad:0x40016C00 width 13. tree "DSI Host Registers" rgroup.long 0x00++0x03 line.long 0x00 "DSI_VR,DSI Host Version Register" group.long 0x04++0x0B line.long 0x00 "DSI_CR,DSI Host Control Register" bitfld.long 0x00 0. " EN , Enable" "Disabled,Enabled" line.long 0x04 "DSI_CCR,DSI HOST Clock Control Register" hexmask.long.byte 0x04 8.--15. 1. " TOCKDIV ,Timeout clock division" hexmask.long.byte 0x04 0.--7. 1. " TXECKDIV ,TX escape clock division" line.long 0x08 "DSI_LVCIDR,DSI Host LTDC VCID Register" bitfld.long 0x08 0.--1. " VCID , Virtual channel ID" "0,1,2,3" if (((per.l(ad:0x40016C00+0x10))&0x0F)==(0x03||0x04)) group.long 0x10++0x03 line.long 0x00 "DSI_LCOLCR,DSI Host LTDC Color Coding Register" bitfld.long 0x00 8. " LPE , Loosely packet enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " COLC , Color Coding" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." else group.long 0x10++0x03 line.long 0x00 "DSI_LCOLCR,DSI Host LTDC Color Coding Register" bitfld.long 0x00 0.--3. " COLC , Color coding" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." endif group.long 0x14++0x07 line.long 0x00 "DSI_LPCR,DSI Host LTDC Polarity Configuration Register" bitfld.long 0x00 2. " HSP ,HSYNC polarity" "High,Low" bitfld.long 0x00 1. " VSP ,VSYNC polarity" "High,Low" bitfld.long 0x00 0. " DEP ,Data enable polarity" "High,Low" line.long 0x04 "DSI_LPMCR,DSI Host Low-Power Mode Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LPSIZE ,Largest packet size" hexmask.long.byte 0x04 0.--7. 1. " VLPSIZE ,VACT largest packet size" group.long 0x2C++0x03 line.long 0x00 "DSI_PCR,DSI Host Protocol Configuration Register" bitfld.long 0x00 4. " CRCRXE ,CRC reception enable" "Disabled,Enabled" bitfld.long 0x00 3. " ECCRXE ,ECC reception enable" "Disabled,Enabled" bitfld.long 0x00 2. " BTAE ,Bus turn around enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ETRXE ,EoTp reception enable" "Disabled,Enabled" bitfld.long 0x00 0. " ETTXE ,EoTp transmission enable" "Disabled,Enabled" group.long 0x30++0x43 line.long 0x00 "DSI_GVCIDR,DSI Host Generic VCID Register" bitfld.long 0x00 0.--1. " VCID ,Virtual channel ID" "0,1,2,3" line.long 0x04 "DSI_MCR,DSI Host mode Configuration Register" bitfld.long 0x04 0. " CMDM ,Command mode" "Video mode,Host mode" line.long 0x08 "DSI_VMCR,DSI Host Video mode Configuration Register" bitfld.long 0x08 24. " PGO ,Pattern generator orientation" "Vertical,Hotizontal" bitfld.long 0x08 20. " PGM ,Pattern generator mode" "Horizontal/Vertical,Vertical" bitfld.long 0x08 16. " PGE ,Pattern generator enable" "Disabled,Enabled" bitfld.long 0x08 15. " LPCE ,Low-power command enable" "Disabled,Enabled" textline " " bitfld.long 0x08 14. " FBTAAE ,Frame bus-turn-around acknowledge enable" "Disabled,Enabled" bitfld.long 0x08 13. " LPHFPE ,Low-power horizontal front-porch enable" "Disabled,Enabled" bitfld.long 0x08 12. " LPHBPE ,Low-power horizontal back-porch enable" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " LPVAE ,Low-power vertical active enable" "Disabled,Enabled" bitfld.long 0x08 10. " LPVFPE ,Low-power vertical front-porch enable" "Disabled,Enabled" bitfld.long 0x08 9. " LPVBPE ,Low-power vertical back-porch enable" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " LPVSAE ,Low-power vertical sync active enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " VMT ,Video mode type" "Non-Burst/sync pulses,Non-Burst/sync events,Burst mode,Burst mode" line.long 0x0C "DSI_VPCR,DSI Host Video Packet Configuration Register" hexmask.long.word 0x0C 0.--13. 1. " VPSIZE ,Video packet size" line.long 0x10 "DSI_VCCR,DSI Host Video Chunks Configuration Register" hexmask.long.word 0x10 0.--13. 1. " NUMC ,Number of chunks" line.long 0x14 "DSI_VNPCR,DSI Host Video Null Packet Configuration Register" hexmask.long.word 0x14 0.--12. 1. " NPSIZE ,Null packet size" line.long 0x18 "DSI_VHSACR,DSI Host Video HSA Configuration Register" hexmask.long.word 0x18 0.--11. 1. " HSA ,Horizontal synchronism active duration" line.long 0x1C "DSI_VHBPCR,DSI Host Video HBP Configuration Register" hexmask.long.word 0x1C 0.--11. 1. " HBP ,Horizontal back-porch duration" line.long 0x20 "DSI_VLCR,DSI Host Video HBP Configuration Register" hexmask.long.word 0x20 0.--14. 1. " HLINE ,Horizontal line duration" line.long 0x24 "DSI_VVSACR,DSI Host Video VSA Configuration Register" hexmask.long.word 0x24 0.--9. 1. " VSA ,Vertical synchronism active duration" line.long 0x28 "DSI_VVBPCR,DSI Host Video VBP Configuration Register" hexmask.long.word 0x28 0.--9. 1. " VBP ,Vertical back-porch duration" line.long 0x2C "DSI_VVFPCR,DSI Host Video VBP Configuration Register" hexmask.long.word 0x2C 0.--9. 1. " VFP ,Vertical front-porch duration" line.long 0x30 "DSI_VVACR,DSI Host Video VA Configuration Register" hexmask.long.word 0x30 0.--13. 1. " VA ,Vertical active duration" line.long 0x34 "DSI_LCCR,DSI Host LTDC Command Configuration Register" hexmask.long.word 0x34 0.--15. 1. " CMDSIZE ,Command size" line.long 0x38 "DSI_CMCR,DSI Host Command mode Configuration Register" bitfld.long 0x38 24. " MRDPS ,Maximum read packet size" "High-speed,Low-power" bitfld.long 0x38 19. " DLWTX ,DCS long write transmission" "High-speed,Low-power" bitfld.long 0x38 18. " DSR0TX ,DCS short read zero parameter transmission" "High-speed,Low-power" bitfld.long 0x38 17. " DSW1TX ,DCS short read one parameter transmission" "High-speed,Low-power" textline " " bitfld.long 0x38 16. " DSW0TX ,DCS short write zero parameter transmission" "High-speed,Low-power" bitfld.long 0x38 14. " GLWTX ,Generic long write transmission" "High-speed,Low-power" bitfld.long 0x38 13. " GSR2TX ,Generic short read two parameters Transmission" "High-speed,Low-power" bitfld.long 0x38 12. " GSR1TX ,Generic short read one parameters transmission" "High-speed,Low-power" textline " " bitfld.long 0x38 11. " GSR0TX ,Generic short read zero parameters transmission" "High-speed,Low-power" bitfld.long 0x38 10. " GSW2TX ,Generic short read one parameters transmission" "High-speed,Low-power" bitfld.long 0x38 9. " GSW1TX ,Generic short write one parameters transmission" "High-speed,Low-power" bitfld.long 0x38 8. " GSW0TX ,Generic short write zero parameters transmission" "High-speed,Low-power" textline " " bitfld.long 0x38 1. " ARE ,Acknowledge request enable" "Disabled,Enabled" bitfld.long 0x38 0. " TEARE ,Tearing effect acknowledge request enable" "Disabled,Enabled" line.long 0x3C "DSI_GHCR,DSI Host Generic Header Configuration Register" hexmask.long.byte 0x3C 16.--23. 1. " WCMSB ,WordCount MSB" hexmask.long.byte 0x3C 8.--15. 1. " WCLSB ,WordCount LSB" bitfld.long 0x3C 6.--7. " VCID ,Channel" "0,1,2,3" bitfld.long 0x3C 0.--5. " DT ,Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "DSI_GPDR,DSI Host Generic Payload Data Register" hexmask.long.byte 0x40 24.--31. 1. " DATA4 ,Payload byte 4" hexmask.long.byte 0x40 16.--23. 1. " DATA3 ,Payload byte 3" hexmask.long.byte 0x40 8.--15. 1. " DATA2 ,Payload byte 2" hexmask.long.byte 0x40 0.--7. 1. " DATA1 ,Payload byte 1" rgroup.long 0x74++0x03 line.long 0x00 "DSI_GPSR,DSI Host Generic Packet Status Register" bitfld.long 0x00 6. " RCB ,Read command busy" "Not busy,Busy" bitfld.long 0x00 5. " PRDFF ,Payload read FIFO FULl" "Not full,Full" bitfld.long 0x00 4. " PRDFE ,Payload read FIFO empty" "Not empty,Empty" bitfld.long 0x00 3. " PWRFF ,Payload write FIFO full" "Not full,Full" textline " " bitfld.long 0x00 2. " PWRFE ,Payload write FIFO empty" "Not empty,Empty" bitfld.long 0x00 1. " CMDFF ,Command FIFO full" "Not full,Full" bitfld.long 0x00 0. " CMDFE ,Command FIFO empty" "Not empty,Empty" group.long 0x78++0x17 line.long 0x00 "DSI_TCCR0,DSI Host Timeout Counter Configuration Register 0" hexmask.long.word 0x00 16.--31. 1. " HSTX_TOCNT ,High-speed transmission timeout counter" hexmask.long.word 0x00 0.--15. 1. " LPRX_TOCNT ,Low-power reception timeout counter" line.long 0x04 "DSI_TCCR1,DSI Host Timeout Counter Configuration Register 1" hexmask.long.word 0x04 0.--15. 1. " HSRD_TOCNT ,High-speed read timeout counter" line.long 0x08 "DSI_TCCR2,DSI Host Timeout Counter Configuration Register 2" hexmask.long.word 0x08 0.--15. 1. " LPRD_TOCNT ,Low-power read timeout counter" line.long 0x0C "DSI_TCCR3,DSI Host Timeout Counter Configuration Register 3" bitfld.long 0x0C 24. " PM ,Presp mode" "Disabled,Enabled" hexmask.long.word 0x0C 0.--15. 1. " HSWR_TOCNT ,High-speed write timeout counter" line.long 0x10 "DSI_TCCR4,DSI Host Timeout Counter Configuration Register 4" hexmask.long.word 0x10 0.--15. 1. " LSWR_TOCNT ,Low-power write timeout counter" line.long 0x14 "DSI_TCCR5,DSI Host Timeout Counter Configuration Register 5" hexmask.long.word 0x14 0.--15. 1. " BTA_TOCNT ,Bus-turn-around timeout counter" group.long 0x94++0x1B line.long 0x00 "DSI_CLCR,DSI Host Clock Lane Configuration Register" bitfld.long 0x00 1. " ACR ,Automatic clock lane control" "Disabled,Enabled" bitfld.long 0x00 0. " DPCC ,D-PHY clock control" "Low-Power,High-Speed" line.long 0x04 "DSI_CLTCR,DSI Host Clock Lane Timer Configuration Register" hexmask.long.word 0x04 16.--25. 1. " HS2LP_TIME ,High-speed to low-power time" hexmask.long.word 0x04 0.--9. 1. " LP2HS_TIME ,Low-power to high-speed time" line.long 0x08 "DSI_DLTCR,DSI Host Data Lane Timer Configuration Register" hexmask.long.byte 0x08 24.--31. 1. " HS2LP_TIME ,High-speed to low-power time" hexmask.long.byte 0x08 16.--23. 1. " LP2HS_TIME ,Low-power to high-speed time" hexmask.long.word 0x08 0.--14. 1. " MRD_TIME ,Maximum read time" line.long 0x0C "DSI_PCTLR,DSI Host PHY Control Register" bitfld.long 0x0C 2. " CKE ,Clock enable" "Disabled,Enabled" bitfld.long 0x0C 1. " DEN ,Digital enable" "Reset,Enabled" line.long 0x10 "DSI_PCONFR,DSI Host PHY Configuration Register" hexmask.long.byte 0x10 8.--15. 1. " SW_TIME ,Stop wait time" bitfld.long 0x10 0.--1. " NL ,Number of lanes" "One data lane,Two data lanes,?..." line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS Control Register" bitfld.long 0x14 3. " UEDL ,ULPS exit on data lane" "No exit,Exit" bitfld.long 0x14 2. " URDL ,ULPS request on data lane" "No request,Request" bitfld.long 0x14 1. " UECL ,ULPS exit on clock lane" "No exit,Exit" bitfld.long 0x14 0. " URCL ,ULPS request on clock lane" "No request,Request" line.long 0x18 "DSI_PTTCR,DSI Host PHY TX Triggers Configuration Register" bitfld.long 0x18 0.--3. " TX_TRIG ,Transmission trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xB0++0x03 line.long 0x00 "DSI_PSR,DSI Host PHY Status Register" bitfld.long 0x00 8. " UAN1 ,ULPS active not lane 1" "Not asserted,Asserted" bitfld.long 0x00 7. " PSS1 ,PHY stop state lane 1" "Not asserted,Asserted" bitfld.long 0x00 6. " RUE0 ,RX ULPS escape lane 0" "Not asserted,Asserted" bitfld.long 0x00 5. " UAN0 ,ULPS active not lane 0" "Not asserted,Asserted" textline " " bitfld.long 0x00 4. " PSS0 ,PHY stop state lane 0" "Not asserted,Asserted" bitfld.long 0x00 3. " UANC ,ULPS active not clock lane" "Not asserted,Asserted" bitfld.long 0x00 2. " PSSC ,PHY stop state clock lane" "Not asserted,Asserted" bitfld.long 0x00 1. " PD ,PHY direction" "Not asserted,Asserted" rgroup.long 0xBC++0x07 line.long 0x00 "DSI_ISR0,DSI Host Interrupt & Status Register 0" bitfld.long 0x00 20. " PE4 ,PHY error 4" "No error,Error" bitfld.long 0x00 19. " PE3 ,PHY error 3" "No error,Error" bitfld.long 0x00 18. " PE2 ,PHY error 2" "No error,Error" textline " " bitfld.long 0x00 17. " PE1 ,PHY error 1" "No error,Error" bitfld.long 0x00 16. " PE0 ,PHY error 0" "No error,Error" bitfld.long 0x00 15. " AE15 ,Acknowledge error 15" "No error,Error" textline " " bitfld.long 0x00 14. " AE14 ,Acknowledge error 14" "No error,Error" bitfld.long 0x00 13. " AE13 ,Acknowledge error 13" "No error,Error" bitfld.long 0x00 12. " AE12 ,Acknowledge error 12" "No error,Error" textline " " bitfld.long 0x00 11. " AE11 ,Acknowledge error 11" "No error,Error" bitfld.long 0x00 10. " AE10 ,Acknowledge error 10" "No error,Error" bitfld.long 0x00 9. " AE9 ,Acknowledge error 9" "No error,Error" textline " " bitfld.long 0x00 8. " AE8 ,Acknowledge error 8" "No error,Error" bitfld.long 0x00 7. " AE7 ,Acknowledge error 7" "No error,Error" bitfld.long 0x00 6. " AE6 ,Acknowledge error 6" "No error,Error" textline " " bitfld.long 0x00 5. " AE5 ,Acknowledge error 5" "No error,Error" bitfld.long 0x00 4. " AE4 ,Acknowledge error 4" "No error,Error" bitfld.long 0x00 3. " AE3 ,Acknowledge error 3" "No error,Error" textline " " bitfld.long 0x00 2. " AE2 ,Acknowledge error 2" "No error,Error" bitfld.long 0x00 1. " AE1 ,Acknowledge error 1" "No error,Error" bitfld.long 0x00 0. " AE0 ,Acknowledge error 0" "No error,Error" line.long 0x04 "DSI_ISR1,DSI Host Interrupt & Status Register 1" bitfld.long 0x04 12. " GPRXE ,Generic payload receive error" "No error,Error" bitfld.long 0x04 11. " GPRDE ,Generic payload read error" "No error,Error" bitfld.long 0x04 10. " GPTXE ,Generic payload transmit error" "No error,Error" textline " " bitfld.long 0x04 9. " GPWRE ,Generic payload write error" "No error,Error" bitfld.long 0x04 8. " GCWRE ,Generic command write error" "No error,Error" bitfld.long 0x04 7. " LPWRE ,LTDC payload write error" "No error,Error" textline " " bitfld.long 0x04 6. " EOTPE ,EoTp error" "No error,Error" bitfld.long 0x04 5. " PSE ,Packet size error" "No error,Error" bitfld.long 0x04 4. " CRCE ,CRC error" "No error,Error" textline " " bitfld.long 0x04 3. " ECCME ,ECC multi-bit error" "No error,Error" bitfld.long 0x04 2. " ECCSE ,ECC single-bit error" "No error,Error" bitfld.long 0x04 1. " TOLPRX ,Timeout low-power reception" "No error,Error" textline " " bitfld.long 0x04 0. " TOHSTX ,Timeout high-speed transmission" "No error,Error" group.long 0xC4++0x07 line.long 0x00 "DSI_IER0,DSI Host Interrupt Enable Register 0" bitfld.long 0x00 20. " PE4IE ,PHY error 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " PE3IE ,PHY error 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " PE2IE ,PHY error 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PE1IE ,PHY error 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " PE0IE ,PHY error 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " AE15IE ,Acknowledge error 15 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " AE14IE ,Acknowledge error 14 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " AE13IE ,Acknowledge error 13 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " AE12IE ,Acknowledge error 12 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " AE11IE ,Acknowledge error 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " AE10IE ,Acknowledge error 10 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " AE9IE ,Acknowledge error 9 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " AE8IE ,Acknowledge error 8 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " AE7IE ,Acknowledge error 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " AE6IE ,Acknowledge error 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " AE5IE ,Acknowledge error 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " AE4IE ,Acknowledge error 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " AE3IE ,Acknowledge error 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " AE2IE ,Acknowledge error 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " AE1IE ,Acknowledge error 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " AE0IE ,Acknowledge error 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "DSI_IER1,DSI Host Interrupt Enable Register 1" bitfld.long 0x04 12. " GPRXEIE ,Generic payload receive error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 11. " GPRDEIE ,Generic payload read error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " GPTXEIE ,Generic payload transmit error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " GPWREIE ,Generic payload write error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 8. " GCWREIE ,Generic command write error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 7. " LPWREIE ,LTDC payload write error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " EOTPEIE ,EoTp error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 5. " PSEIE ,Packet size error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 4. " CRCEIE ,CRC error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " ECCMEIE ,ECC multi-bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 2. " ECCSEIE ,ECC single-bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " TOLPRXIE ,Timeout low-power reception interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " TOHSTXIE ,Timeout high-speed transmission interrupt enable" "Disabled,Enabled" wgroup.long 0xD8++0x07 line.long 0x00 "DSI_FIR0,DSI Host Force Interrupt Register 0" bitfld.long 0x00 20. " FPE4 ,Force PHY error 4" "No effect,Force error" bitfld.long 0x00 19. " FPE3 ,Force PHY error 3" "No effect,Force error" bitfld.long 0x00 18. " FPE2 ,Force PHY error 2" "No effect,Force error" textline " " bitfld.long 0x00 17. " FPE1 ,Force PHY error 1" "No effect,Force error" bitfld.long 0x00 16. " FPE0 ,Force PHY error 0" "No effect,Force error" bitfld.long 0x00 15. " FAE15 ,Force acknowledge error 15" "No effect,Force error" textline " " bitfld.long 0x00 14. " FAE14 ,Force acknowledge error 14" "No effect,Force error" bitfld.long 0x00 13. " FAE13 ,Force acknowledge error 13" "No effect,Force error" bitfld.long 0x00 12. " FAE12 ,Force acknowledge error 12" "No effect,Force error" textline " " bitfld.long 0x00 11. " FAE11 ,Force acknowledge error 11" "No effect,Force error" bitfld.long 0x00 10. " FAE10 ,Force acknowledge error 10" "No effect,Force error" bitfld.long 0x00 9. " FAE9 ,Force acknowledge error 9" "No effect,Force error" textline " " bitfld.long 0x00 8. " FAE8 ,Force acknowledge error 8" "No effect,Force error" bitfld.long 0x00 7. " FAE7 ,Force acknowledge error 7" "No effect,Force error" bitfld.long 0x00 6. " FAE6 ,Force acknowledge error 6" "No effect,Force error" textline " " bitfld.long 0x00 5. " FAE5 ,Force acknowledge error 5" "No effect,Force error" bitfld.long 0x00 4. " FAE4 ,Force acknowledge error 4" "No effect,Force error" bitfld.long 0x00 3. " FAE3 ,Force acknowledge error 3" "No effect,Force error" textline " " bitfld.long 0x00 2. " FAE2 ,Force acknowledge error 2" "No effect,Force error" bitfld.long 0x00 1. " FAE1 ,Force acknowledge error 1" "No effect,Force error" bitfld.long 0x00 0. " FAE0 ,Force acknowledge error 0" "No effect,Force error" line.long 0x04 "DSI_FIR1,DSI Host Force Interrupt Register 1" bitfld.long 0x04 12. " FGPRXE ,Generic payload receive error force" "No effect,Force error" bitfld.long 0x04 11. " FGPRDE ,Generic payload read error force" "No effect,Force error" bitfld.long 0x04 10. " FGPTXE ,Generic payload transmit error force" "No effect,Force error" textline " " bitfld.long 0x04 9. " FGPWRE ,Generic payload write error force" "No effect,Force error" bitfld.long 0x04 8. " FGCWRE ,Generic command write error force" "No effect,Force error" bitfld.long 0x04 7. " FLPWRE ,LTDC payload write error force" "No effect,Force error" textline " " bitfld.long 0x04 6. " FEOTPE ,EoTp error force" "No effect,Force error" bitfld.long 0x04 5. " FPSE ,Packet size error force" "No effect,Force error" bitfld.long 0x04 4. " FCRCE ,CRC error force" "No effect,Force error" textline " " bitfld.long 0x04 3. " FECCME ,ECC multi-bit error force" "No effect,Force error" bitfld.long 0x04 2. " FECCSE ,ECC single-bit error force" "No effect,Force error" bitfld.long 0x04 1. " FTOLPRX ,Timeout low-power reception force" "No effect,Force error" textline " " bitfld.long 0x04 0. " FTOHSTX ,Timeout high-speed transmission force" "No effect,Force error" group.long 0x100++0x03 line.long 0x00 "DSI_VSCR,DSI Host Video Shadow Control Register" bitfld.long 0x00 8. " UR ,Update register" "No update,Update" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x10C++0x03 line.long 0x00 "DSI_LCVCIDR,DSI Host LTDC Current VCID Register" bitfld.long 0x00 0.--1. " VCID ,Virtual channel ID" "0,1,2,3" if (((per.l(ad:0x40016C00+0x34))&0x01)==0x01) rgroup.long 0x110++0x03 line.long 0x00 "DSI_LCCCR,DSI Host LTDC Current Color Coding Register" bitfld.long 0x00 8. " LPE ,Loosely packed enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " COLC , Color coding" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit,24-bit" else rgroup.long 0x110++0x03 line.long 0x00 "DSI_LCCCR,DSI Host LTDC Current Color Coding Register" bitfld.long 0x00 8. " LPE ,Loosely packed enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " COLC , Color coding" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." endif rgroup.long 0x118++0x03 line.long 0x00 "DSI_LPMCCR,DSI Host Low-Power mode Current Configuration Register" hexmask.long.byte 0x00 16.--23. 1. " LPSIZE ,Largest packet size" hexmask.long.byte 0x00 0.--7. 1. " VLPSIZE ,VACT largest packet size" rgroup.long 0x138++0x2B line.long 0x00 "DSI_VMCCR,DSI Host Video mode Current Configuration Register" bitfld.long 0x00 9. " LPCE ,Low-power command enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " FBTAAE ,Frame bus-turn-around acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 7. " LPHFE ,Low-power horizontal front-porch enable" "Disabled,Enabled" bitfld.long 0x00 6. " LPHBPE ,Low-power horizontal back-porch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " LPVAE ,Low-power vertical active enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPVFPE ,Low-power vertical front-porch enable" "Disabled,Enabled" bitfld.long 0x00 3. " LPVBPE ,Low-power vertical back-porch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LPVSAE ,Low-power vertical sync active enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VMT ,Video mode type" "Non-Burst/sync pulses,Non-Burst/sync events,Burst mode,Burst mode" line.long 0x04 "DSI_VPCCR,DSI Host Video Packet Current Configuration Register" hexmask.long.word 0x04 0.--13. 1. " VPSIZE ,Video packet size" line.long 0x08 "DSI_VCCCR,DSI Host Video Chunks Current Configuration Register" hexmask.long.word 0x08 0.--13. 1. " NUMC ,Number of chunks" line.long 0x0C "DSI_VNPCCR,DSI Host Video Null Packet Current Configuration Register" hexmask.long.word 0x0C 0.--12. 1. " NPSIZE ,Null packet size" line.long 0x10 "DSI_VHSACCR,DSI Host Video HSA Current Configuration Register" hexmask.long.word 0x10 0.--11. 1. " HSA ,Horizontal synchronism active duration" line.long 0x14 "DSI_VHBPCCR,DSI Host Video HBP Current Configuration Register" hexmask.long.word 0x14 0.--11. 1. " HBP ,Horizontal back-porch duration" line.long 0x18 "DSI_VLCCR,DSI Host Video Line Current Configuration Register" hexmask.long.word 0x18 0.--14. 1. " HLINE ,Horizontal line duration" line.long 0x1C "DSI_VVSACCR,DSI Host Video VSA Current Configuration Register" hexmask.long.word 0x1C 0.--9. 1. " VSA ,Vertical synchronism active duration" line.long 0x20 "DSI_VVBPCCR,DSI Host Video VBP Current Configuration Register" hexmask.long.word 0x20 0.--9. 1. " VBP ,Vertical back-porch duration" line.long 0x24 "DSI_VVFPCCR,DSI Host Video VFP Current Configuration Register" hexmask.long.word 0x24 0.--9. 1. " VFP ,Vertical front-porch duration" line.long 0x28 "DSI_VVACCR,DSI Host Video VA Current Configuration Register" hexmask.long.word 0x28 0.--13. 1. " VA ,Vertical active duration" tree.end width 11. tree "DSI Wrapper Registers" if (((per.l(ad:0x40016C00+0x100))&0x01)==0x00) if (((per.l(ad:0x40016C00+0x404))&0x04)==0x00) group.long 0x400++0x03 line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register" bitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling edge,Rising edge" bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled" bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising edge,Falling edge" textline " " bitfld.long 0x00 4. " TESRC ,TE source" "DSI Link,External pin" bitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." bitfld.long 0x00 0. " DSIM ,DSI mode" "Video mode,Adapted Command mode" else group.long 0x400++0x03 line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register" rbitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling edge,Rising edge" bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled" bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising edge,Falling edge" textline " " bitfld.long 0x00 4. " TESRC ,TE source" "DSI Link,External pin" rbitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." bitfld.long 0x00 0. " DSIM ,DSI mode" "Video mode,Adapted Command mode" endif else if (((per.l(ad:0x40016C00+0x404))&0x04)==0x00) group.long 0x400++0x03 line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register" bitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling edge,Rising edge" rbitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled" rbitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising edge,Falling edge" textline " " rbitfld.long 0x00 4. " TESRC ,TE source" "DSI Link,External pin" bitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." rbitfld.long 0x00 0. " DSIM ,DSI mode" "Video mode,Adapted Command mode" else rgroup.long 0x400++0x03 line.long 0x00 "DSI_WCFGR,DSI Wrapper Configuration Register" bitfld.long 0x00 7. " VSPOL ,VSync polarity" "Falling edge,Rising edge" bitfld.long 0x00 6. " AR ,Automatic refresh" "Disabled,Enabled" bitfld.long 0x00 5. " TEPOL ,TE polarity" "Rising edge,Falling edge" textline " " bitfld.long 0x00 4. " TESRC ,TE source" "DSI Link,External pin" bitfld.long 0x00 1.--3. " COLMUX ,Color multiplexing" "16-bit configuration 1,16-bit configuration 2,16-bit configuration 3,18-bit configuration 1,18-bit configuration 2,24-bit,?..." bitfld.long 0x00 0. " DSIM ,DSI mode" "Video mode,Adapted Command mode" endif endif group.long 0x404++0x07 line.long 0x00 "DSI_WCR,DSI Wrapper Control Register" bitfld.long 0x00 3. " DSIEN ,DSI enable" "Disabled,Enabled" bitfld.long 0x00 2. " LTDCEN ,LTDC enable" "Disabled,Enabled" bitfld.long 0x00 1. " SHTDN ,Shutdown" "Display ON,Display OFF" bitfld.long 0x00 0. " COLM ,Color mode" "Full color,Eight color" line.long 0x04 "DSI_WIER,DSI Wrapper Interrupt Enable Register" bitfld.long 0x04 13. " RRIE ,Regulator ready interrupt enable" "Disabled,Enabled" bitfld.long 0x04 10. " PLLUIE ,PLL unlock interrupt enable" "Disabled,Enabled" bitfld.long 0x04 9. " PLLLIE ,PLL lock interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " ERIE ,End of refresh interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " TEIE ,Tearing effect interrupt enable" "Disabled,Enabled" rgroup.long 0x40C++0x03 line.long 0x00 "DSI_WISR,DSI Wrapper Interrupt & Status Register" bitfld.long 0x00 13. " RRIF ,Regulator ready interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 12. " RRS ,Regulator ready status" "Not ready,Ready" bitfld.long 0x00 10. " PLLUIF ,PLL unlock interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 9. " PLLLIF ,PLL lock interrupt flag" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " PLLLS ,PLL lock status" "Unlocked,Locked" bitfld.long 0x00 2. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 1. " ERIF ,End of refresh interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " TEIF ,Tearing effect interrupt flag" "No interrupt,Interrupt" group.long 0x410++0x03 line.long 0x00 "DSI_WIFCR,DSI Wrapper Interrupt Flag Clear Register" eventfld.long 0x00 13. " CRRIF ,Clear regulator ready interrupt flag" "No effect,Clear" eventfld.long 0x00 10. " CPLLUIF ,Clear PLL unlock interrupt flag" "No effect,Clear" eventfld.long 0x00 9. " CPLLLIF ,Clear PLL lock interrupt flag" "No effect,Clear" textline " " eventfld.long 0x00 1. " CERIF ,Clear end of refresh interrupt flag" "No effect,Clear" eventfld.long 0x00 0. " CTEIF ,Clear tearing effect interrupt flag" "No effect,Clear" group.long 0x418++0x03 line.long 0x00 "DSI_WPCR0,DSI Wrapper PHY Configuration Register 0" bitfld.long 0x00 27. " TCLKPOSTEN ,Custom time for tCLK-POST enable" "Disabled,Enabled" bitfld.long 0x00 26. " TLPXCEN ,Custom time for tLPX for clock lane enable" "Disabled,Enabled" bitfld.long 0x00 25. " THSEXITEN ,Custom time for tHS-EXIT enable" "Disabled,Enabled" bitfld.long 0x00 24. " TLPXDEN ,Custom time for tLPX for data lanes enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " THSZEROEN ,Custom time for tHS-ZERO enable" "Disabled,Enabled" bitfld.long 0x00 22. " THSTRAILEN ,Custom time for tHS-TRAIL Enable" "Disabled,Enabled" bitfld.long 0x00 21. " THSPREPEN ,Custom time for tHS-PREPARE enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCLKZEROEN ,Custom time for tCLK-ZERO enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " TCLKPREPEN ,Custom time for tCLK-PREPARE enable" "Disabled,Enabled" bitfld.long 0x00 18. " PDEN ,Pull-down enable" "Disabled,Enabled" bitfld.long 0x00 16. " TDDL ,Turn disable data lanes" "No effect,RX mode" bitfld.long 0x00 14. " CDOFFDL ,Contention detection off on data lanes" "Data lane ON,Data lane OFF" textline " " bitfld.long 0x00 13. " FTXSMDL ,Force data lanes in TX stop mode" "No effect,TX mode" bitfld.long 0x00 12. " FTXSMCL ,Force clock lane in TX Stop mode" "No effect,TX mode" bitfld.long 0x00 11. " HSIDL1 ,Invert the high-speed data signal on data lane 1" "Normal,Inverted" bitfld.long 0x00 10. " HSIDL0 ,Invert the high-speed data signal on data lane 0" "Normal,Inverted" textline " " bitfld.long 0x00 9. " HSICL ,Invert high-speed data signal on clock lane" "Normal,Inverted" bitfld.long 0x00 8. " SWDL1 ,Swap data lane 1 pins" "Regular clock,Swapped clock" bitfld.long 0x00 7. " SWDL0 ,Swap data lane 0 pins" "Regular clock,Swapped clock" bitfld.long 0x00 6. " SWCL ,Swap clock lane pins" "Regular clock,Swapped clock" textline " " bitfld.long 0x00 0.--5. " UIX4 ,Unit Interval multiplied by 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0x40016C00+0x100))&0x01)==0x00)&&(((per.l(ad:0x40016C00+0x404))&0x04)==0x00) group.long 0x41C++0x0F line.long 0x00 "DSI_WPCR1,DSI Wrapper PHY Configuration Register 1" bitfld.long 0x00 25.--26. " LPRXFT ,Low-power rx low-pass filtering tuning" "0,1,2,3" bitfld.long 0x00 22. " FLPRXLPM ,Force lp receiver in low-power mode" "No effect,Low-Power mode" bitfld.long 0x00 18.--19. " HSTXSRCDL ,High-speed transmission slew rate control on data lanes" "0,1,2,3" bitfld.long 0x00 16.--17. " HSTXSRCCL ,High-speed transmission slew rate control on clock lane" "0,1,2,3" textline " " bitfld.long 0x00 12. " SDDC ,SDD control" "No effect,Activated" bitfld.long 0x00 8.--9. " LPSRCDL ,Low-power transmission slew rate compensation on data lanes" "0,1,2,3" bitfld.long 0x00 6.--7. " LPSRCCL ,Low-power transmission slew rate compensation on clock lane" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " HSTXDDL ,High-speed transmission delay on data lanes" "0,1,2,3" bitfld.long 0x00 0.--1. " HSTXDCL ,High-speed transmission delay on clock lane" "0,1,2,3" line.long 0x04 "DSI_WPCR2,DSI Wrapper PHY Configuration Register 2" hexmask.long.byte 0x04 24.--31. 1. " THSTRAIL ,tHSTRAIL" hexmask.long.byte 0x04 16.--23. 1. " THSPREP ,tHS-PREPARE" hexmask.long.byte 0x04 8.--15. 1. " TCLKZERO ,tCLK-ZERO" hexmask.long.byte 0x04 0.--7. 1. " TCLKPREP ,tCLK-PREPARE" line.long 0x08 "DSI_WPCR3,DSI Wrapper PHY Configuration Register 3" hexmask.long.byte 0x08 24.--31. 1. " TLPXC ,tLPXC for clock lane" hexmask.long.byte 0x08 16.--23. 1. " THSEXIT ,tHSEXIT" hexmask.long.byte 0x08 8.--15. 1. " TLPXD ,tLPX for data lanes" hexmask.long.byte 0x08 0.--7. 1. " THSZERO ,tHS-ZERO" line.long 0x0C "DSI_WPCR4,DSI Wrapper PHY Configuration Register 4" hexmask.long.byte 0x0C 0.--7. 1. " TCLKPOST ,tCLK-POST" else rgroup.long 0x41C++0x0F line.long 0x00 "DSI_WPCR1,DSI Wrapper PHY Configuration Register 1" bitfld.long 0x00 25.--26. " LPRXFT ,Low-power RX low-pass filtering tuning" "0,1,2,3" bitfld.long 0x00 22. " FLPRXLPM ,Force LP receiver in low-power mode" "No effect,Low-Power mode" bitfld.long 0x00 18.--19. " HSTXSRCDL ,High-speed transmission slew rate control on data lanes" "0,1,2,3" bitfld.long 0x00 16.--17. " HSTXSRCCL ,High-speed transmission slew rate control on clock lane" "0,1,2,3" textline " " bitfld.long 0x00 12. " SDDC ,SDD control" "No effect,Activated" bitfld.long 0x00 8.--9. " LPSRCDL ,Low-power transmission slew rate compensation on data lanes" "0,1,2,3" bitfld.long 0x00 6.--7. " LPSRCCL ,Low-power transmission slew rate compensation on clock lane" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " HSTXDDL ,High-speed transmission delay on data lanes" "0,1,2,3" bitfld.long 0x00 0.--1. " HSTXDCL ,High-speed transmission delay on clock lane" "0,1,2,3" line.long 0x04 "DSI_WPCR2,DSI Wrapper PHY Configuration Register 2" hexmask.long.byte 0x04 24.--31. 1. " THSTRAIL ,tHSTRAIL" hexmask.long.byte 0x04 16.--23. 1. " THSPREP ,tHS-PREPARE" hexmask.long.byte 0x04 8.--15. 1. " TCLKZERO ,tCLK-ZERO" hexmask.long.byte 0x04 0.--7. 1. " TCLKPREP ,tCLK-PREPARE" line.long 0x08 "DSI_WPCR3,DSI Wrapper PHY Configuration Register 3" hexmask.long.byte 0x08 24.--31. 1. " TLPXC ,tLPXC for clock lane" hexmask.long.byte 0x08 16.--23. 1. " THSEXIT ,tHSEXIT" hexmask.long.byte 0x08 8.--15. 1. " TLPXD ,tLPX for data lanes" hexmask.long.byte 0x08 0.--7. 1. " THSZERO ,tHS-ZERO" line.long 0x0C "DSI_WPCR4,DSI Wrapper PHY Configuration Register 4" hexmask.long.byte 0x0C 0.--7. 1. " TCLKPOST ,tCLK-POST" endif group.long 0x430++0x03 line.long 0x00 "DSI_WRPCR,DSI Wrapper Regulator And PLL Control Register" bitfld.long 0x00 24. " REGEN ,Regulator enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " ODF ,PLL output division factor" "/1,/2,/4,/8" bitfld.long 0x00 11.--14. " IDF ,PLL input division factor" "/1,/2,/3,/4,/5,/6,/7,?..." hexmask.long.byte 0x00 2.--8. 1. " NDIV ,PLL loop division factor" textline " " bitfld.long 0x00 0. " PLLEN ,PLL enable" "Disabled,Enabled" tree.end width 0x0B tree.end endif sif (!cpuis("STM32F446*")&&!cpuis("STM32F411*")&&!cpuis("STM32F401*")) tree "RNG (Random Number Generator)" sif cpuis("STM32F410*") base ad:0x40080000 else base ad:0x50060800 endif width 8. group.long 0x00++0x7 line.long 0x00 "RNG_CR,RNG Control Register" sif (cpuis("STM32F7*")||cpuis("STM32F4*")||cpuis("STM32F20*")) bitfld.long 0x00 3. " IE ,Interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 3. " IM ,Interrupt mask" "Disabled,Enabled" endif bitfld.long 0x00 2. " RNGEN ,Random number generator enable" "Disabled,Enabled" line.long 0x04 "RNG_SR,RNG Status Register" bitfld.long 0x04 6. " SEIS ,Seed error interrupt status" "No error,Error" bitfld.long 0x04 5. " CEIS ,Clock error interrupt status" "No error,Error" textline " " rbitfld.long 0x04 2. " SECS ,Seed error current status" "No error,Error" rbitfld.long 0x04 1. " CECS ,Clock error current status" "No error,Error" textline " " rbitfld.long 0x04 0. " DRDY ,Data ready" "Not ready,Ready" hgroup.long 0x08++0x3 hide.long 0x00 "RNG_DR,RNG Data Register" in width 0xB tree.end endif sif cpuis("STM32F415*")||cpuis("STM32F417*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F479*") tree "CRYP (Cryptographic Processor)" base ad:0x50060000 width 17. if (((per.l(ad:0x50060000+0x04))&0x10)==0x10) sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) group.long 0x00++0x3 line.long 0x00 "CRYP_CR,CRYP control register" bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final" bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled" rbitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush" rbitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..." textline " " rbitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit" rbitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,GCM,CCM,?..." rbitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption" else group.long 0x00++0x3 line.long 0x00 "CRYP_CR,CRYP control register" bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled" rbitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush" rbitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..." rbitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit" textline " " rbitfld.long 0x00 3.--5. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key" rbitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption" endif else sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) group.long 0x00++0x3 line.long 0x00 "CRYP_CR,CRYP control register" bitfld.long 0x00 16.--17. " GCM_CCMPH ,GCM_CCM phase" "Init,Header,Payload,Final" bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled" bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush" bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..." textline " " bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit" bitfld.long 0x00 3.--5. 19. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key,GCM,CCM,?..." bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption" else group.long 0x00++0x3 line.long 0x00 "CRYP_CR,CRYP control register" bitfld.long 0x00 15. " CRYPEN ,Cryptographic processor enable" "Disabled,Enabled" bitfld.long 0x00 14. " FFLUSH ,FIFO flush" "No effect,Flush" bitfld.long 0x00 8.--9. " KEYSIZE ,Key size selection (AES mode only)" "128-bit,192-bit,256-bit,?..." bitfld.long 0x00 6.--7. " DATATYPE ,Data type selection" "32-bit,16-bit,8-bit,1-bit" textline " " bitfld.long 0x00 3.--5. " ALGOMODE ,Algorithm mode" "TDES-ECB,TDES-CBC,DES-ECB,DES-CBC,AES-ECB,AES-CBC,AES-CTR,AES-Key" bitfld.long 0x00 2. " ALGODIR ,Algorithm direction" "Encryption,Decryption" endif endif rgroup.long 0x04++0x3 line.long 0x00 "CRYP_SR,CRYP Status Register" bitfld.long 0x00 4. " BUSY ,Busy bit" "Not busy,Busy" bitfld.long 0x00 3. " OFFU ,Output FIFO full" "Not full,Full" bitfld.long 0x00 2. " OFNE ,Output FIFO not empty" "Empty,Not empty" bitfld.long 0x00 1. " IFNF ,Input FIFO not full" "Full,Not full" textline " " bitfld.long 0x00 0. " IFEM ,Input FIFO empty" "Not empty,Empty" hgroup.long 0x08++0x3 hide.long 0x00 "CRYP_DIN,CRYP Data Input Register" in hgroup.long 0x0C++0x3 hide.long 0x00 "CRYP_DOUT,CRYP Data Output Register" in group.long 0x10++0x07 line.long 0x00 "CRYP_DMACR,CRYP DMA Control Register" bitfld.long 0x00 1. " DOEN ,DMA output enable" "Disabled,Enabled" bitfld.long 0x00 0. " DIEN ,DMA input enable" "Disabled,Enabled" line.long 0x04 "CRYP_IMSCR,CRYP Interrupt Mask Set/Clear Register" bitfld.long 0x04 1. " OUTIM ,Output FIFO service interrupt mask" "Masked,Not masked" bitfld.long 0x04 0. " INIM ,Input FIFO service interrupt mask" "Masked,Not masked" rgroup.long 0x18++0x7 line.long 0x00 "CRYP_RISR,CRYP Raw Interrupt Status Register" bitfld.long 0x00 1. " OUTRIS ,Output FIFO service raw interrupt status" "Not pending,Pending" bitfld.long 0x00 0. " INRIS ,Input FIFO service raw interrupt status" "Not pending,Pending" line.long 0x04 "CRYP_MISR,CRYP Masked Interrupt Status Register" bitfld.long 0x04 1. " OUTMIS ,Output FIFO service masked interrupt status" "Not pending,Pending" bitfld.long 0x04 0. " INMIS ,Input FIFO service masked interrupt status" "Not pending,Pending" wgroup.long 0x20++0x1F line.long 0x00 "CRYP_K0LR,Key 0 Leftmost Register" line.long 0x04 "CRYP_K0RR,Key 0 Rightmost Register" line.long 0x08 "CRYP_K1LR,Key 1 Leftmost Register" line.long 0x0C "CRYP_K1RR,Key 1 Rightmost Register" line.long 0x10 "CRYP_K2LR,Key 2 Leftmost Register" line.long 0x14 "CRYP_K2RR,Key 2 Rightmost Register" line.long 0x18 "CRYP_K3LR,Key 3 Leftmost Register" line.long 0x1C "CRYP_K3RR,Key 3 Rightmost Register" if (((per.l(ad:0x50060000+0x04))&0x10)==0x10) rgroup.long 0x40++0xF line.long 0x00 "CRYP_IV0LR,Initialization Vector 0 Leftmost Register" line.long 0x04 "CRYP_IV0RR,Initialization Vector 0 Rightmost Register" line.long 0x08 "CRYP_IV1LR,Initialization Vector 1 Leftmost Register" line.long 0x0C "CRYP_IV1RR,Initialization Vector 1 Rightmost Register" else group.long 0x40++0xF line.long 0x00 "CRYP_IV0LR,Initialization Vector 0 Leftmost Register" line.long 0x04 "CRYP_IV0RR,Initialization Vector 0 Rightmost Register" line.long 0x08 "CRYP_IV1LR,Initialization Vector 1 Leftmost Register" line.long 0x0C "CRYP_IV1RR,Initialization Vector 1 Rightmost Register" endif sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")) if ((((per.l(ad:0x50060000))&0x80038)==0x80000)||(((per.l(ad:0x50060000))&0x80038)==0x80008)) group.long 0x50++0x1F line.long 0x00 "CRYP_CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC" line.long 0x04 "CRYP_CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC" line.long 0x08 "CRYP_CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC" line.long 0x0c "CRYP_CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC" line.long 0x10 "CRYP_CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC" line.long 0x14 "CRYP_CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC" line.long 0x18 "CRYP_CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC" line.long 0x1c "CRYP_CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC" else hgroup.long 0x50++0x1F hide.long 0x00 "CRYP_CSGCMCCM0R,Context Swap Register 0 For GCM/GMAC Or CCM/CMAC" hide.long 0x04 "CRYP_CSGCMCCM1R,Context Swap Register 1 For GCM/GMAC Or CCM/CMAC" hide.long 0x08 "CRYP_CSGCMCCM2R,Context Swap Register 2 For GCM/GMAC Or CCM/CMAC" hide.long 0x0c "CRYP_CSGCMCCM3R,Context Swap Register 3 For GCM/GMAC Or CCM/CMAC" hide.long 0x10 "CRYP_CSGCMCCM4R,Context Swap Register 4 For GCM/GMAC Or CCM/CMAC" hide.long 0x14 "CRYP_CSGCMCCM5R,Context Swap Register 5 For GCM/GMAC Or CCM/CMAC" hide.long 0x18 "CRYP_CSGCMCCM6R,Context Swap Register 6 For GCM/GMAC Or CCM/CMAC" hide.long 0x1c "CRYP_CSGCMCCM7R,Context Swap Register 7 For GCM/GMAC Or CCM/CMAC" endif if (((per.l(ad:0x50060000))&0x80038)==0x80000) group.long 0x70++0x1F line.long 0x00 "CRYP_CSGCM0R,Context Swap Register 0 For GCM/GMAC" line.long 0x04 "CRYP_CSGCM1R,Context Swap Register 1 For GCM/GMAC" line.long 0x08 "CRYP_CSGCM2R,Context Swap Register 2 For GCM/GMAC" line.long 0x0c "CRYP_CSGCM3R,Context Swap Register 3 For GCM/GMAC" line.long 0x10 "CRYP_CSGCM4R,Context Swap Register 4 For GCM/GMAC" line.long 0x14 "CRYP_CSGCM5R,Context Swap Register 5 For GCM/GMAC" line.long 0x18 "CRYP_CSGCM6R,Context Swap Register 6 For GCM/GMAC" line.long 0x1c "CRYP_CSGCM7R,Context Swap Register 7 For GCM/GMAC" else hgroup.long 0x70++0x1F hide.long 0x00 "CRYP_CSGCM0R,Context Swap Register 0 For GCM/GMAC" hide.long 0x04 "CRYP_CSGCM1R,Context Swap Register 1 For GCM/GMAC" hide.long 0x08 "CRYP_CSGCM2R,Context Swap Register 2 For GCM/GMAC" hide.long 0x0c "CRYP_CSGCM3R,Context Swap Register 3 For GCM/GMAC" hide.long 0x10 "CRYP_CSGCM4R,Context Swap Register 4 For GCM/GMAC" hide.long 0x14 "CRYP_CSGCM5R,Context Swap Register 5 For GCM/GMAC" hide.long 0x18 "CRYP_CSGCM6R,Context Swap Register 6 For GCM/GMAC" hide.long 0x1c "CRYP_CSGCM7R,Context Swap Register 7 For GCM/GMAC" endif endif width 0xB tree.end endif sif cpuis("STM32F415*")||cpuis("STM32F417*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F479*") tree "HASH (Hash Processor)" base ad:0x50060400 width 10. if (((per.l(ad:0x50060400))&0x1000)==0x1000) group.long 0x00++0xB line.long 0x00 "HASH_CR,HASH Control Register" bitfld.long 0x00 16. " LKEY ,Long key selection" "Short,Long" sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) textline " " bitfld.long 0x00 13. " MDMAT ,Multiple DMA Transfers" "Single,Multiple" endif textline " " rbitfld.long 0x00 12. " DINNE ,DIN not empty" "Empty,Not empty" rbitfld.long 0x00 8.--11. " NBW ,Number of words already pushed" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) bitfld.long 0x00 7. 18. " ALGO ,Algorithm selection" "SHA-1,MD5,SHA224,SHA256" textline " " else bitfld.long 0x00 7. " ALGO ,Algorithm selection" "SHA-1,MD5" textline " " endif bitfld.long 0x00 6. " MODE ,Mode selection" "Hash,HMAC" bitfld.long 0x00 4.--5. " DATATYPE ,Data type selection" "32-bit data,16-bit data,8-bit data,Bit data" bitfld.long 0x00 3. " DMAE ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " INIT ,Initialize message digest calculation" "No effect,Initialize" line.long 0x04 "HASH_DIN,HASH Data Input Register" line.long 0x08 "HASH_STR,HASH Start Register" bitfld.long 0x08 8. " DCAL ,Digest calculation" "No effect,Start" bitfld.long 0x08 0.--4. " NBLW ,Number of valid bits in the last word of the message" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x00++0xB line.long 0x00 "HASH_CR,HASH Control Register" bitfld.long 0x00 16. " LKEY ,Long key selection" "Short,Long" sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) textline " " bitfld.long 0x00 13. " MDMAT ,Multiple DMA Transfers" "Single,Multiple" endif textline " " rbitfld.long 0x00 12. " DINNE ,DIN not empty" "Empty,Not empty" rbitfld.long 0x00 8.--11. " NBW ,Number of words already pushed" "0,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) bitfld.long 0x00 7. 18. " ALGO ,Algorithm selection" "SHA-1,MD5,SHA224,SHA256" textline " " else bitfld.long 0x00 7. " ALGO ,Algorithm selection" "SHA-1,MD5" textline " " endif bitfld.long 0x00 6. " MODE ,Mode selection" "Hash,HMAC" bitfld.long 0x00 4.--5. " DATATYPE ,Data type selection" "32-bit data,16-bit data,8-bit data,Bit data" bitfld.long 0x00 3. " DMAE ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 2. " INIT ,Initialize message digest calculation" "No effect,Initialize" line.long 0x04 "HASH_DIN,HASH Data Input Register" line.long 0x08 "HASH_STR,HASH Start Register" bitfld.long 0x08 8. " DCAL ,Digest calculation" "No effect,Start" bitfld.long 0x08 0.--4. " NBLW ,Number of valid bits in the last word of the message" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x0C++0x13 line.long 0x00 "HASH_HR0,HASH Digest Register H0" line.long 0x04 "HASH_HR1,HASH Digest Register H1" line.long 0x08 "HASH_HR2,HASH Digest Register H2" line.long 0x0C "HASH_HR3,HASH Digest Register H3" line.long 0x10 "HASH_HR4,HASH Digest Register H4" rgroup.long 0x310++0x13 line.long 0x00 "HASH_HR0,HASH Digest Register H0" line.long 0x04 "HASH_HR1,HASH Digest Register H1" line.long 0x08 "HASH_HR2,HASH Digest Register H2" line.long 0x0C "HASH_HR3,HASH Digest Register H3" line.long 0x10 "HASH_HR4,HASH Digest Register H4" sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) rgroup.long 0x324++0x0B line.long 0x00 "HASH_HR5,HASH Digest Register H5" line.long 0x04 "HASH_HR6,HASH Digest Register H6" line.long 0x08 "HASH_HR7,HASH Digest Register H7" endif group.long 0x20++0x7 line.long 0x00 "HASH_IMR,HASH Interrupt Mask Register" sif (cpuis("STM32F405*")||cpuis("STM32F407*")||cpuis("STM32F41*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F479*")||cpuis("STM32F7*")) bitfld.long 0x00 1. " DCIE ,Digest calculation completion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " DINIE ,Data input interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 1. " DCIM ,Digest calculation completion interrupt mask" "Disabled,Enabled" bitfld.long 0x00 0. " DINIM ,Data input interrupt mask" "Disabled,Enabled" endif line.long 0x04 "HASH_SR,HASH Status Register" rbitfld.long 0x04 3. " BUSY ,Busy bit" "Not busy,Busy" rbitfld.long 0x04 2. " DMAS ,DMA interface/transfer status" "Disabled/No transfer,Enabled/Transfer" bitfld.long 0x04 1. " DCIS ,Digest calculation completion interrupt status" "Not completed,Completed" bitfld.long 0x04 0. " DINIS ,Data input interrupt status" "Not ready,Ready" tree "HASH context swap registers" width 12. group.long 0xF8++0xCB line.long 0x0 "HASH_CSR0,HASH Context Swap Register 0" line.long 0x4 "HASH_CSR1,HASH Context Swap Register 1" line.long 0x8 "HASH_CSR2,HASH Context Swap Register 2" line.long 0xC "HASH_CSR3,HASH Context Swap Register 3" line.long 0x10 "HASH_CSR4,HASH Context Swap Register 4" line.long 0x14 "HASH_CSR5,HASH Context Swap Register 5" line.long 0x18 "HASH_CSR6,HASH Context Swap Register 6" line.long 0x1C "HASH_CSR7,HASH Context Swap Register 7" line.long 0x20 "HASH_CSR8,HASH Context Swap Register 8" line.long 0x24 "HASH_CSR9,HASH Context Swap Register 9" line.long 0x28 "HASH_CSR10,HASH Context Swap Register 10" line.long 0x2C "HASH_CSR11,HASH Context Swap Register 11" line.long 0x30 "HASH_CSR12,HASH Context Swap Register 12" line.long 0x34 "HASH_CSR13,HASH Context Swap Register 13" line.long 0x38 "HASH_CSR14,HASH Context Swap Register 14" line.long 0x3C "HASH_CSR15,HASH Context Swap Register 15" line.long 0x40 "HASH_CSR16,HASH Context Swap Register 16" line.long 0x44 "HASH_CSR17,HASH Context Swap Register 17" line.long 0x48 "HASH_CSR18,HASH Context Swap Register 18" line.long 0x4C "HASH_CSR19,HASH Context Swap Register 19" line.long 0x50 "HASH_CSR20,HASH Context Swap Register 20" line.long 0x54 "HASH_CSR21,HASH Context Swap Register 21" line.long 0x58 "HASH_CSR22,HASH Context Swap Register 22" line.long 0x5C "HASH_CSR23,HASH Context Swap Register 23" line.long 0x60 "HASH_CSR24,HASH Context Swap Register 24" line.long 0x64 "HASH_CSR25,HASH Context Swap Register 25" line.long 0x68 "HASH_CSR26,HASH Context Swap Register 26" line.long 0x6C "HASH_CSR27,HASH Context Swap Register 27" line.long 0x70 "HASH_CSR28,HASH Context Swap Register 28" line.long 0x74 "HASH_CSR29,HASH Context Swap Register 29" line.long 0x78 "HASH_CSR30,HASH Context Swap Register 30" line.long 0x7C "HASH_CSR31,HASH Context Swap Register 31" line.long 0x80 "HASH_CSR32,HASH Context Swap Register 32" line.long 0x84 "HASH_CSR33,HASH Context Swap Register 33" line.long 0x88 "HASH_CSR34,HASH Context Swap Register 34" line.long 0x8C "HASH_CSR35,HASH Context Swap Register 35" line.long 0x90 "HASH_CSR36,HASH Context Swap Register 36" line.long 0x94 "HASH_CSR37,HASH Context Swap Register 37" line.long 0x98 "HASH_CSR38,HASH Context Swap Register 38" line.long 0x9C "HASH_CSR39,HASH Context Swap Register 39" line.long 0xA0 "HASH_CSR40,HASH Context Swap Register 40" line.long 0xA4 "HASH_CSR41,HASH Context Swap Register 41" line.long 0xA8 "HASH_CSR42,HASH Context Swap Register 42" line.long 0xAC "HASH_CSR43,HASH Context Swap Register 43" line.long 0xB0 "HASH_CSR44,HASH Context Swap Register 44" line.long 0xB4 "HASH_CSR45,HASH Context Swap Register 45" line.long 0xB8 "HASH_CSR46,HASH Context Swap Register 46" line.long 0xBC "HASH_CSR47,HASH Context Swap Register 47" line.long 0xC0 "HASH_CSR48,HASH Context Swap Register 48" line.long 0xC4 "HASH_CSR49,HASH Context Swap Register 49" line.long 0xC8 "HASH_CSR50,HASH Context Swap Register 50" sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F7*")||cpuis("STM32F479*")) group.long 0x1C4++0x0B line.long 0x00 "HASH_CSR51,HASH Context Swap Register 51" line.long 0x04 "HASH_CSR52,HASH Context Swap Register 52" line.long 0x08 "HASH_CSR53,HASH Context Swap Register 53" endif tree.end width 0xB tree.end endif tree.open "ACT (Advanced-control Timers)" tree "TIM 1" base ad:0x40010000 width 12. if (((per.w(ad:0x40010000))&0x60)>0)||((((per.w(ad:0x40010000+0x08))&0x7)>=0x1)&&(((per.w(ad:0x40010000+0x08))&0x7)<=0x3)) group.word 0x00++0x1 line.word 0x00 "TIM1_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM1_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif if (((per.l(ad:0x40010000+0x44))&0x300)!=0x0) group.word 0x04++0x1 line.word 0x00 "TIM1_CR2,Control register 2" rbitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1" rbitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1" rbitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1" textline " " rbitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1" rbitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1" rbitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1" textline " " rbitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" textline " " bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update" bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge" bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded" else group.word 0x04++0x1 line.word 0x00 "TIM1_CR2,Control register 2" bitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1" bitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1" bitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1" textline " " bitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1" bitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1" bitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1" textline " " bitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" textline " " bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update" bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge" bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded" endif if (((per.l(ad:0x40010000+0x8))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM1_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" textline " " sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6") rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF" textline " " else rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM1_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" textline " " sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6") bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF" textline " " else bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM1_DIER,DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM1_SR,Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt Flag" "No break,Break" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM1_EGR,Event generation register" bitfld.word 0x00 7. " BG ,Break Generation" "No effect,Generate" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No effect,Generate" textline " " bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.l(ad:0x40010000+0x44))&0x300)==0x300) if (((per.w((ad:0x40010000+0x18)))&0x303)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40010000+0x18)))&0x003)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010000+0x18)))&0x003)!=0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif else if (((per.w((ad:0x40010000+0x18)))&0x303)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40010000+0x18)))&0x003)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010000+0x18)))&0x003)!=0x000) if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.w((ad:0x40010000+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif endif if (((per.l(ad:0x40010000+0x44))&0x300)==0x300) if (((per.w((ad:0x40010000+0x1C)))&0x303)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40010000+0x1C)))&0x003)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40010000+0x1C)))&0x003)!=0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif else if (((per.w((ad:0x40010000+0x1C)))&0x303)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40010000+0x1C)))&0x003)==0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010000+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40010000+0x1C)))&0x003)!=0x000) if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.w((ad:0x40010000+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010000+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif endif sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " if (((per.w(ad:0x40010000+0x44))&0x300)==(0x200||0x300)) if (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010000+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010000+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif textline " " else group.word 0x20++0x1 line.word 0x00 "TIM1_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output Polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Off,On" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Not inverted,Inverted" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output Polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Off,On" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM1_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM1_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM1_ARR,Auto-reload register" group.word 0x30++0x1 line.word 0x00 "TIM1_RCR,Repetition counter register" hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition Counter Value" group.word 0x34++0x1 line.word 0x00 "TIM1_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM1_CCR2,Capture/compare register 2" group.word 0x3C++0x1 line.word 0x00 "TIM1_CCR3,Capture/compare register 3" group.word 0x40++0x1 line.word 0x00 "TIM1_CCR4,Capture/compare register 4" if (((per.l(ad:0x40010000+0x44))&0x300)==0x100) group.word 0x44++0x1 line.word 0x00 "TIM1_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" rbitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" rbitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" elif (((per.l(ad:0x40010000+0x44))&0x300)==0x200) group.word 0x44++0x1 line.word 0x00 "TIM1_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" rbitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" rbitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" else group.word 0x44++0x1 line.word 0x00 "TIM1_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" endif group.word 0x48++0x1 line.word 0x00 "TIM1_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,?..." group.word 0x4C++0x1 line.word 0x00 "TIM1_DMAR,DMA address for burst mode" width 0x0B tree.end sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")) tree "TIM 8" base ad:0x40010400 width 12. if (((per.w(ad:0x40010400))&0x60)>0)||((((per.w(ad:0x40010400+0x08))&0x7)>=0x1)&&(((per.w(ad:0x40010400+0x08))&0x7)<=0x3)) group.word 0x00++0x1 line.word 0x00 "TIM8_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM8_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif if (((per.l(ad:0x40010400+0x44))&0x300)!=0x0) group.word 0x04++0x1 line.word 0x00 "TIM8_CR2,Control register 2" rbitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1" rbitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1" rbitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1" textline " " rbitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1" rbitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1" rbitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1" textline " " rbitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" textline " " bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update" bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge" bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded" else group.word 0x04++0x1 line.word 0x00 "TIM8_CR2,Control register 2" bitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1" bitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1" bitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1" textline " " bitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1" bitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1" bitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1" textline " " bitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" textline " " bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update" bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge" bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded" endif if (((per.l(ad:0x40010400+0x8))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM8_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" textline " " sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6") rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF" textline " " else rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM8_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" textline " " sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6") bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF" textline " " else bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM8_DIER,DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM8_SR,Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 7. " BIF ,Break interrupt Flag" "No break,Break" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" textline " " bitfld.word 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM8_EGR,Event generation register" bitfld.word 0x00 7. " BG ,Break Generation" "No effect,Generate" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No effect,Generate" textline " " bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.l(ad:0x40010400+0x44))&0x300)==0x300) if (((per.w((ad:0x40010400+0x18)))&0x303)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40010400+0x18)))&0x003)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010400+0x18)))&0x003)!=0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif else if (((per.w((ad:0x40010400+0x18)))&0x303)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40010400+0x18)))&0x003)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40010400+0x18)))&0x003)!=0x000) if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.w((ad:0x40010400+0x20)))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif endif if (((per.l(ad:0x40010400+0x44))&0x300)==0x300) if (((per.w((ad:0x40010400+0x1C)))&0x303)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40010400+0x1C)))&0x003)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40010400+0x1C)))&0x003)!=0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif else if (((per.w((ad:0x40010400+0x1C)))&0x303)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40010400+0x1C)))&0x003)==0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40010400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40010400+0x1C)))&0x003)!=0x000) if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared" rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.w((ad:0x40010400+0x20)))&0x1100)==0x00) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.w((ad:0x40010400+0x20)))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif endif sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " if (((per.w(ad:0x40010400+0x44))&0x300)==(0x200||0x300)) if (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else if (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x303)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)!=0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" elif (((per.w(ad:0x40010400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40010400+0x18))&0x03)==0x00) group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif endif textline " " else group.word 0x20++0x1 line.word 0x00 "TIM8_CCER,Capture/compare enable register" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output Polarity" "High,Low" bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Off,On" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Not inverted,Inverted" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output Polarity" "High,Low" bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Off,On" textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Not inverted,Inverted" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM8_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM8_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM8_ARR,Auto-reload register" group.word 0x30++0x1 line.word 0x00 "TIM8_RCR,Repetition counter register" hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition Counter Value" group.word 0x34++0x1 line.word 0x00 "TIM8_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM8_CCR2,Capture/compare register 2" group.word 0x3C++0x1 line.word 0x00 "TIM8_CCR3,Capture/compare register 3" group.word 0x40++0x1 line.word 0x00 "TIM8_CCR4,Capture/compare register 4" if (((per.l(ad:0x40010400+0x44))&0x300)==0x100) group.word 0x44++0x1 line.word 0x00 "TIM8_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" rbitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" rbitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" elif (((per.l(ad:0x40010400+0x44))&0x300)==0x200) group.word 0x44++0x1 line.word 0x00 "TIM8_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" rbitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" rbitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" else group.word 0x44++0x1 line.word 0x00 "TIM8_BDTR,Break and dead-time register" bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled" bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled" bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High" textline " " bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled" bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled" bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced" textline " " bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3" hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up" endif group.word 0x48++0x1 line.word 0x00 "TIM8_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..." bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM8_CR1,TIM8_CR2,TIM8_SMCR,TIM8_DIER,TIM8_SR,TIM8_EGR,TIM8_CCMR1,TIM8_CCMR2,TIM8_CCER,TIM8_CNT,TIM8_PSC,TIM8_ARR,TIM8_RCR,TIM8_CCR1,TIM8_CCR2,TIM8_CCR3,TIM8_CCR4,TIM8_BDTR,TIM8_DCR,TIM8_DMAR,?..." group.word 0x4C++0x1 line.word 0x00 "TIM8_DMAR,DMA address for burst mode" width 0x0B tree.end endif tree.end tree.open "GPT (General-purpose Timers)" sif !cpuis("STM32F410*") tree "TIM 2" base ad:0x40000000 width 12. if (((per.l(ad:0x40000000))&0x60)!=0x00)||(((per.l(ad:0x40000000+0x08))&0x03)==(0x01||0x02||0x03)) group.word 0x00++0x1 line.word 0x00 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM2_CR1,TIM2 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x1 line.word 0x00 "TIM2_CR2,TIM2 Control register 2" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC2,Update" if (((per.w(ad:0x40000000+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM2_SMCR,TIM2 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM2_SMCR,TIM2 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM2_DIER,TIM2 DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM2_SR,TIM2 Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM2_EGR,TIM2 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000) if (((per.l(ad:0x40000000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0) if (((per.l(ad:0x40000000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000) if (((per.l(ad:0x40000000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40000000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000) if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000000+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0) if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)!=0x0) if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.l(ad:0x40000000+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000000+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif (cpuis("STM32F4*")) if ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000000+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000000+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM2_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On" textline " " bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On" endif textline " " sif cpuis("STM32F2*")||cpuis("STM32F4*") group.long 0x24++0x3 line.long 0x00 "TIM2_CNT,Counter" hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Low counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value" group.word 0x28++0x1 line.word 0x00 "TIM2_PSC,Prescaler" group.long 0x2C++0x3 line.long 0x00 "TIM2_ARR,Auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" group.long 0x34++0x0F line.long 0x00 "TIM2_CCR1,Capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM2_CCR2,Capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM2_CCR3,Capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0C "TIM2_CCR4,Capture/compare register 4" hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" else group.word 0x24++0x1 line.word 0x00 "TIM2_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM2_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM2_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM2_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM2_CCR2,Capture/compare register 2" endif textline " " group.word 0x48++0x1 line.word 0x00 "TIM2_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,?..." group.word 0x4C++0x1 line.word 0x00 "TIM2_DMAR,DMA address for full transfer" textline "" sif (cpuis("STM32F2*")) group.word 0x50++0x3 line.word 0x00 "TIM2_OR,TIM2 option register" bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input" textline " " elif (cpuis("STM32F401*")||cpuis("STM32F411*")) group.word 0x50++0x3 line.word 0x00 "TIM2_OR,TIM2 option register" bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" ",PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input" textline " " elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*")) group.word 0x50++0x3 line.word 0x00 "TIM2_OR,TIM2 option register" bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input" textline " " elif (cpuis("STM32F4*")) group.word 0x50++0x3 line.word 0x00 "TIM2_OR,TIM2 option register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input" else bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP trigger output is connected to TIM2_ITR1,OTG FS SOF is connected to the TIM2_ITR1 input,OTG HS SOF is connected to the TIM2_ITR1 input" endif textline " " elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) group.word 0x50++0x01 line.word 0x00 "TIM2_OR,TIM2 option register" bitfld.word 0x00 0. " TR1_RMP ,Timer 2 Internal trigger 1 remap" "TIM2 ITR1 input is connected to TIM10 OC,TIM2 ITR1 input is connected to TIM5 TGO" textline " " endif width 0x0B tree.end tree "TIM 3" base ad:0x40000400 width 12. if (((per.l(ad:0x40000400))&0x60)!=0x00)||(((per.l(ad:0x40000400+0x08))&0x03)==(0x01||0x02||0x03)) group.word 0x00++0x1 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM3_CR1,TIM3 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x1 line.word 0x00 "TIM3_CR2,TIM3 Control register 2" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC3,Update" if (((per.w(ad:0x40000400+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM3_SMCR,TIM3 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM3_DIER,TIM3 DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM3_SR,TIM3 Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM3_EGR,TIM3 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40000400+0x18)))&0x303)==0x000) if (((per.l(ad:0x40000400+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000400+0x18)))&0x3)==0x0) if (((per.l(ad:0x40000400+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000400+0x18)))&0x300)==0x000) if (((per.l(ad:0x40000400+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40000400+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif if (((per.w((ad:0x40000400+0x1C)))&0x303)==0x000) if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0) if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)!=0x0) if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.l(ad:0x40000400+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000400+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif (cpuis("STM32F4*")) if ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000400+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000400+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM3_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On" textline " " bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On" endif textline " " sif cpuis("STM32F2*")||cpuis("STM32F4*") group.long 0x24++0x3 line.long 0x00 "TIM3_CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Low counter value" group.word 0x28++0x1 line.word 0x00 "TIM3_PSC,Prescaler" group.long 0x2C++0x3 line.long 0x00 "TIM3_ARR,Auto-reload register" hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x34++0xF line.long 0x00 "TIM3_CCR1,Capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,Capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value" line.long 0x08 "TIM3_CCR3,Capture/compare register 3" hexmask.long.word 0x04 0.--15. 1. " CCR3 ,Low Capture/Compare 3 value" line.long 0x0C "TIM3_CCR4,Capture/compare register 4" hexmask.long.word 0x04 0.--15. 1. " CCR4 ,Low Capture/Compare 4 value" else group.long 0x34++0x7 line.long 0x00 "TIM3_CCR1,Capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value" line.long 0x04 "TIM3_CCR2,Capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value" endif else group.word 0x24++0x1 line.word 0x00 "TIM3_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM3_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM3_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM3_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM3_CCR2,Capture/compare register 2" endif textline " " group.word 0x48++0x1 line.word 0x00 "TIM3_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,?..." group.word 0x4C++0x1 line.word 0x00 "TIM3_DMAR,DMA address for full transfer" textline "" sif (cpuis("STM32F2*")) group.word 0x50++0x3 line.word 0x00 "TIM3_OR,TIM3 option register" elif (cpuis("STM32F401*")||cpuis("STM32F411*")) elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*")) elif (cpuis("STM32F4*")) elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) group.word 0x50++0x01 line.word 0x00 "TIM3_OR,TIM3 option register" bitfld.word 0x00 0. " TR1_RMP ,Timer 2 Internal trigger 1 remap" "TIM3 ITR2 input is connected to TIM11 OC,TIM3 ITR2 input is connected to TIM5 TGO" textline " " endif width 0x0B tree.end tree "TIM 4" base ad:0x40000800 width 12. if (((per.l(ad:0x40000800))&0x60)!=0x00)||(((per.l(ad:0x40000800+0x08))&0x03)==(0x01||0x02||0x03)) group.word 0x00++0x1 line.word 0x00 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM4_CR1,TIM4 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x1 line.word 0x00 "TIM4_CR2,TIM4 Control register 2" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC4,Update" if (((per.w(ad:0x40000800+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM4_SMCR,TIM4 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM4_SMCR,TIM4 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM4_DIER,TIM4 DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM4_SR,TIM4 Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM4_EGR,TIM4 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40000800+0x18)))&0x303)==0x000) if (((per.l(ad:0x40000800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000800+0x18)))&0x3)==0x0) if (((per.l(ad:0x40000800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000800+0x18)))&0x300)==0x000) if (((per.l(ad:0x40000800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40000800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif if (((per.w((ad:0x40000800+0x1C)))&0x303)==0x000) if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000800+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0) if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)!=0x0) if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.l(ad:0x40000800+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000800+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif (cpuis("STM32F4*")) if ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000800+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000800+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM4_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On" textline " " bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On" endif textline " " sif cpuis("STM32F2*")||cpuis("STM32F4*") group.long 0x24++0x3 line.long 0x00 "TIM4_CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " CNT ,Low counter value" group.word 0x28++0x1 line.word 0x00 "TIM4_PSC,Prescaler" group.long 0x2C++0x3 line.long 0x00 "TIM4_ARR,Auto-reload register" hexmask.long.word 0x00 0.--15. 1. " ARR ,Low auto-reload value" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x34++0xF line.long 0x00 "TIM4_CCR1,Capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value" line.long 0x04 "TIM4_CCR2,Capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value" line.long 0x08 "TIM4_CCR3,Capture/compare register 3" hexmask.long.word 0x04 0.--15. 1. " CCR3 ,Low Capture/Compare 3 value" line.long 0x0C "TIM4_CCR4,Capture/compare register 4" hexmask.long.word 0x04 0.--15. 1. " CCR4 ,Low Capture/Compare 4 value" else group.long 0x34++0x7 line.long 0x00 "TIM4_CCR1,Capture/compare register 1" hexmask.long.word 0x00 0.--15. 1. " CCR1 ,Low Capture/Compare 1 value" line.long 0x04 "TIM4_CCR2,Capture/compare register 2" hexmask.long.word 0x04 0.--15. 1. " CCR2 ,Low Capture/Compare 2 value" endif else group.word 0x24++0x1 line.word 0x00 "TIM4_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM4_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM4_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM4_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM4_CCR2,Capture/compare register 2" endif textline " " group.word 0x48++0x1 line.word 0x00 "TIM4_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,?..." group.word 0x4C++0x1 line.word 0x00 "TIM4_DMAR,DMA address for full transfer" textline "" sif (cpuis("STM32F2*")) group.word 0x50++0x3 line.word 0x00 "TIM4_OR,TIM4 option register" elif (cpuis("STM32F401*")||cpuis("STM32F411*")) elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*")) elif (cpuis("STM32F4*")) elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) endif width 0x0B tree.end endif tree "TIM 5" base ad:0x40000C00 width 12. if (((per.l(ad:0x40000C00))&0x60)!=0x00)||(((per.l(ad:0x40000C00+0x08))&0x03)==(0x01||0x02||0x03)) group.word 0x00++0x1 line.word 0x00 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" else group.word 0x00++0x1 line.word 0x00 "TIM5_CR1,TIM5 control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3" textline " " bitfld.word 0x00 4. " DIR ,Direction" "Up,Down" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" endif group.word 0x04++0x1 line.word 0x00 "TIM5_CR2,TIM5 Control register 2" bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF" bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC5,Update" if (((per.w(ad:0x40000C00+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM5_SMCR,TIM5 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F410*")&&!cpuis("STM32F412*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" else group.word 0x08++0x1 line.word 0x00 "TIM5_SMCR,TIM5 Slave mode control register" sif cpuis("STM32F410*") bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." else bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" textline " " bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF" endif textline " " sif (!cpuis("STM32F446*")&&(cpu()!="STM32F405RG")&&(cpu()!="STM32F405VG")&&(cpu()!="STM32F405ZG")&&(cpu()!="STM32F407VE")&&(cpu()!="STM32F407VG")&&(cpu()!="STM32F407ZE")&&(cpu()!="STM32F407ZG")&&(cpu()!="STM32F407IE")&&(cpu()!="STM32F407IG")&&(cpu()!="STM32F415RG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F415VG")&&(cpu()!="STM32F417VE")&&(cpu()!="STM32F417VG")&&(cpu()!="STM32F417ZE")&&(cpu()!="STM32F417ZG")&&(cpu()!="STM32F417IE")&&(cpu()!="STM32F417IG")&&cpu()!="STM32F405OG"&&cpu()!="STM32F405OE"&&cpu()!="STM32F415OG"&&!cpuis("STM32F401*")&&!cpuis("STM32F42*")&&!cpuis("STM32F43*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")) bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF" textline " " endif bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock" endif group.word 0x0C++0x1 line.word 0x00 "TIM5_DIER,TIM5 DMA/Interrupt enable register" bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled" bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM5_SR,TIM5 Status register" bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM5_EGR,TIM5 Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate" bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40000C00+0x18)))&0x303)==0x000) if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000C00+0x18)))&0x3)==0x0) if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40000C00+0x18)))&0x300)==0x000) if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40000C00+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif if (((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000) if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0) if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" sif !cpuis("STM32F410*") bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear" endif textline " " bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif elif (((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)!=0x0) if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" sif cpuis("STM32F410*") bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" else bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear" bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" endif textline " " bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled" bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif else if (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x0100) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" elif (((per.l(ad:0x40000C00+0x20))&0x1100)==0x1000) group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" else group.word 0x1C++0x1 line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2" bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 10.--11. " IC4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " bitfld.word 0x00 2.--3. " IC3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC" endif endif sif (cpuis("STM32F446*")||cpu()=="STM32F405RG"||cpu()=="STM32F405VG"||cpu()=="STM32F405ZG"||cpu()=="STM32F407IE"||cpu()=="STM32F407IG"||cpu()=="STM32F407VE"||cpu()=="STM32F407VG"||cpu()=="STM32F407ZE"||cpu()=="STM32F407ZG"||cpu()=="STM32F415RG"||cpu()=="STM32F415VG"||cpu()=="STM32F415ZG"||cpu()=="STM32F417IE"||cpu()=="STM32F417IG"||cpu()=="STM32F417VE"||cpu()=="STM32F417VG"||cpu()=="STM32F417ZE"||cpu()=="STM32F417ZG"||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,1" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,1" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif (cpuis("STM32F4*")) if ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 complementary output Polarity" "0,?..." bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)!=0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 complementary output Polarity" "0,?..." bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" elif ((((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)&&(((per.w((ad:0x40000C00+0x1C)))&0x303)!=0x000)) group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM5_CCER,Capture/compare enable register" bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled" bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On" textline " " bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On" endif textline " " sif cpuis("STM32F2*")||cpuis("STM32F4*") group.long 0x24++0x3 line.long 0x00 "TIM5_CNT,Counter" hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Low counter value" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value" group.word 0x28++0x1 line.word 0x00 "TIM5_PSC,Prescaler" group.long 0x2C++0x3 line.long 0x00 "TIM5_ARR,Auto-reload register" hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value" hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low auto-reload value" group.long 0x34++0x0F line.long 0x00 "TIM5_CCR1,Capture/compare register 1" hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare 1 value" hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low Capture/Compare 1 value" line.long 0x04 "TIM5_CCR2,Capture/compare register 2" hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High Capture/Compare 2 value" hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low Capture/Compare 2 value" line.long 0x08 "TIM5_CCR3,Capture/compare register 3" hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High Capture/Compare 3 value" hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low Capture/Compare 3 value" line.long 0x0C "TIM5_CCR4,Capture/compare register 4" hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High Capture/Compare 4 value" hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low Capture/Compare 4 value" else group.word 0x24++0x1 line.word 0x00 "TIM5_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM5_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM5_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM5_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM5_CCR2,Capture/compare register 2" endif textline " " group.word 0x48++0x1 line.word 0x00 "TIM5_DCR,DMA control register" bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,?..." bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,?..." group.word 0x4C++0x1 line.word 0x00 "TIM5_DMAR,DMA address for full transfer" textline "" sif (cpuis("STM32F2*")) group.word 0x50++0x3 line.word 0x00 "TIM5_OR,TIM5 option register" bitfld.word 0x00 6.--7. " ITR1_RMP ,Internal trigger 1 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input" textline " " elif (cpuis("STM32F401*")||cpuis("STM32F411*")) group.word 0x50++0x3 line.word 0x00 "TIM5_OR,TIM5 option register" bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input" textline " " elif (cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F446*")) group.word 0x50++0x3 line.word 0x00 "TIM5_OR,TIM5 option register" bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input" textline " " elif (cpuis("STM32F4*")) group.word 0x50++0x3 line.word 0x00 "TIM5_OR,TIM5 option register" bitfld.word 0x00 6.--7. " TI4_RMP ,Timer Input 4 remap" "TIM5 Channel4 is connected to the GPIO,LSI internal clock is connected to the TIM5_CH4 input,LSE internal clock is connected to the TIM5_CH4 input,RTC output event is connected to the TIM5_CH4 input" textline " " elif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) endif width 0x0B tree.end tree "TIM 9" base ad:0x40014000 width 12. group.word 0x00++0x1 line.word 0x00 "TIM9_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3" bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" textline " " endif bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" textline " " sif !cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow" textline " " endif bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM9_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..." endif if (((per.l(ad:0x40014000+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM9_SMCR,Slave mode control register" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " endif bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock" textline " " else bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock" endif else group.word 0x08++0x1 line.word 0x00 "TIM9_SMCR,Slave mode control register" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " endif bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock" textline " " else bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock" endif endif group.word 0x0C++0x1 line.word 0x00 "TIM9_DIER,DMA/Interrupt enable register" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM9_SR,Status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM9_EGR,Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000) if (((per.l(ad:0x40014000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40014000+0x18)))&0x300)!=0x0)&&(((per.w((ad:0x40014000+0x18)))&0x3)==0x0) if (((per.l(ad:0x40014000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014000+0x18)))&0x03)!=0x00) if (((per.l(ad:0x40014000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40014000+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40014000+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000) group.word 0x20++0x1 line.word 0x00 "TIM9_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014000+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM9_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014000+0x18)))&0x3)!=0x0) group.word 0x20++0x1 line.word 0x00 "TIM9_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM9_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM9_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM9_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM9_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM9_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM9_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM9_CCR2,Capture/compare register 2" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) group.word 0x50++0x1 line.word 0x00 "TIM9_OR,TIM9 option register 1" bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O" bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO" endif width 0xB tree.end sif !cpuis("STM32F410*") tree "TIM 10" base ad:0x40014400 width 12. group.word 0x00++0x1 line.word 0x00 "TIM10_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow" else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" endif textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x08++0x1 line.word 0x00 "TIM10_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6")) bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" endif elif (cpuis("STM32F2*")) hgroup.word 0x08++0x1 hide.word 0x00 "TIM10_SMCR,Slave mode control register" elif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM10_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..." endif sif cpuis("STM32F4*") group.word 0x0C++0x1 line.word 0x00 "TIM10_DIER,DMA/Interrupt enable register" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" endif group.word 0x10++0x1 line.word 0x00 "TIM10_SR,Status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM10_EGR,Event generation register" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40014400+0x20)))&0x1)==0x1) if (((per.w((ad:0x40014400+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else if (((per.w((ad:0x40014400+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40014400+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM10_CCER,Capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM10_CCER,Capture/compare enable register" bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM10_CCER,Capture/compare enable register" sif (cpuis("STM32F4*")) bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges" textline " " else bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" textline " " endif bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM10_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM10_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM10_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM10_CCR1,Capture/compare register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x50++0x1 line.word 0x00 "TIM10_OR,TIM10 option register 1" sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) bitfld.word 0x00 3. " TI1_RMP_RI ,Timer10 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI" bitfld.word 0x00 2. " ETR_RMP ,Timer10 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO" textline " " endif bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 Input 1 remapping capability" "TIM10CH1->GPIO,LSE EC->TIM10CH1,LSE EC->TIM10CH1,RTC OE->TIM10CH1" elif (cpuis("STM32F2*")) elif (cpuis("STM32F4*")) endif width 0xB tree.end endif tree "TIM 11" base ad:0x40014800 width 12. group.word 0x00++0x1 line.word 0x00 "TIM11_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow" else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" endif textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x08++0x1 line.word 0x00 "TIM11_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6")) bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" endif elif (cpuis("STM32F2*")) hgroup.word 0x08++0x1 hide.word 0x00 "TIM11_SMCR,Slave mode control register" elif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM11_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..." endif sif cpuis("STM32F4*") group.word 0x0C++0x1 line.word 0x00 "TIM11_DIER,DMA/Interrupt enable register" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" endif group.word 0x10++0x1 line.word 0x00 "TIM11_SR,Status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM11_EGR,Event generation register" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40014800+0x20)))&0x1)==0x1) if (((per.w((ad:0x40014800+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else if (((per.w((ad:0x40014800+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40014800+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM11_CCER,Capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM11_CCER,Capture/compare enable register" bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM11_CCER,Capture/compare enable register" sif (cpuis("STM32F4*")) bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges" textline " " else bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" textline " " endif bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM11_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM11_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM11_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM11_CCR1,Capture/compare register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x50++0x1 line.word 0x00 "TIM11_OR,TIM11 option register 1" sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) bitfld.word 0x00 3. " TI1_RMP_RI ,Timer11 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI" bitfld.word 0x00 2. " ETR_RMP ,Timer11 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO" textline " " endif bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,MSI IC->TIM11CH1,HSE EC->TIM9CH1,TIM11CH1->GPIO" elif (cpuis("STM32F2*")) group.word 0x50++0x1 line.word 0x00 "TIM11_OR,TIM11 option register 1" bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE IC->TIM11CH1,TIM11CH1->GPIO" textline " " elif (cpuis("STM32F4*")) group.word 0x50++0x1 line.word 0x00 "TIM11_OR,TIM11 option register 1" bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE RTC->TIM11CH1,TIM11CH1->GPIO" textline " " endif width 0xB tree.end sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")) tree "TIM 12" base ad:0x40001800 width 12. group.word 0x00++0x1 line.word 0x00 "TIM12_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")) bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3" bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter" textline " " endif bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" textline " " sif !cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" textline " " else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow" textline " " endif bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM12_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..." endif if (((per.l(ad:0x40001800+0x08))&0x07)!=0x0) group.word 0x08++0x1 line.word 0x00 "TIM12_SMCR,Slave mode control register" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " endif bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock" textline " " else bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock" endif else group.word 0x08++0x1 line.word 0x00 "TIM12_SMCR,Slave mode control register" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " endif bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..." textline " " sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")) bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock" textline " " else bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock" endif endif group.word 0x0C++0x1 line.word 0x00 "TIM12_DIER,DMA/Interrupt enable register" bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x1 line.word 0x00 "TIM12_SR,Status register" bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger" bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM12_EGR,Event generation register" bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate" bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate" textline " " bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000) if (((per.l(ad:0x40001800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40001800+0x18)))&0x300)!=0x0)&&(((per.w((ad:0x40001800+0x18)))&0x3)==0x0) if (((per.l(ad:0x40001800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" textline " " bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x03)!=0x00) if (((per.l(ad:0x40001800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear" textline " " endif bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2" bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" textline " " bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif else if (((per.l(ad:0x40001800+0x20))&0x11)==0x00) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10) group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" else group.word 0x18++0x1 line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*")) bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " else bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " endif rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC" endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000) group.word 0x20++0x1 line.word 0x00 "TIM12_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM12_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x3)!=0x0) group.word 0x20++0x1 line.word 0x00 "TIM12_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..." bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM12_CCER,Capture/compare enable register" bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM12_CCER,Capture/compare enable register" bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,1" bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges" textline " " bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..." textline " " bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges" bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM12_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM12_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM12_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM12_CCR1,Capture/compare register 1" group.word 0x38++0x1 line.word 0x00 "TIM12_CCR2,Capture/compare register 2" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")) group.word 0x50++0x1 line.word 0x00 "TIM12_OR,TIM12 option register 1" bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O" bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO" endif width 0xB tree.end tree "TIM 13" base ad:0x40001C00 width 12. group.word 0x00++0x1 line.word 0x00 "TIM13_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow" else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" endif textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x08++0x1 line.word 0x00 "TIM13_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6")) bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" endif elif (cpuis("STM32F2*")) hgroup.word 0x08++0x1 hide.word 0x00 "TIM13_SMCR,Slave mode control register" elif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM13_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..." endif sif cpuis("STM32F4*") group.word 0x0C++0x1 line.word 0x00 "TIM13_DIER,DMA/Interrupt enable register" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" endif group.word 0x10++0x1 line.word 0x00 "TIM13_SR,Status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM13_EGR,Event generation register" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40001C00+0x20)))&0x1)==0x1) if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM13_CCER,Capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM13_CCER,Capture/compare enable register" bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM13_CCER,Capture/compare enable register" sif (cpuis("STM32F4*")) bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges" textline " " else bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" textline " " endif bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM13_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM13_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM13_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM13_CCR1,Capture/compare register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x50++0x1 elif (cpuis("STM32F2*")) elif (cpuis("STM32F4*")) endif width 0xB tree.end tree "TIM 14" base ad:0x40002000 width 12. group.word 0x00++0x1 line.word 0x00 "TIM14_CR1,Control register 1" bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..." bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" textline " " sif cpuis("STM32F4*") bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow" else bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request" endif textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" textline " " bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x08++0x1 line.word 0x00 "TIM14_SMCR,Slave mode control register" bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling" bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8" bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" textline " " sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6")) bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed" endif elif (cpuis("STM32F2*")) hgroup.word 0x08++0x1 hide.word 0x00 "TIM14_SMCR,Slave mode control register" elif (!cpuis("STM32F4*")) group.word 0x04++0x1 line.word 0x00 "TIM14_CR2,Control register 2" bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..." endif sif cpuis("STM32F4*") group.word 0x0C++0x1 line.word 0x00 "TIM14_DIER,DMA/Interrupt enable register" bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" endif group.word 0x10++0x1 line.word 0x00 "TIM14_SR,Status register" bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred" bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched" textline " " bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update" wgroup.word 0x14++0x1 line.word 0x00 "TIM14_EGR,Event generation register" bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate" bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate" if (((per.w((ad:0x40002000+0x20)))&0x1)==0x1) if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0) group.word 0x18++0x1 line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared" textline " " endif bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive" bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled" textline " " sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." textline " " else bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif else group.word 0x18++0x1 line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1" bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8" bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events" textline " " bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..." endif endif sif cpuis("STM32F4*") if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0) group.word 0x20++0x1 line.word 0x00 "TIM14_CCER,Capture/compare enable register" bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..." bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" else group.word 0x20++0x1 line.word 0x00 "TIM14_CCER,Capture/compare enable register" bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both" textline " " bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled" endif else group.word 0x20++0x1 line.word 0x00 "TIM14_CCER,Capture/compare enable register" sif (cpuis("STM32F4*")) bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges" textline " " else bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge" textline " " endif bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled" endif group.word 0x24++0x1 line.word 0x00 "TIM14_CNT,Counter" group.word 0x28++0x1 line.word 0x00 "TIM14_PSC,Prescaler" group.word 0x2C++0x1 line.word 0x00 "TIM14_ARR,Auto-reload register" group.word 0x34++0x1 line.word 0x00 "TIM14_CCR1,Capture/compare register 1" sif (cpuis("STM32L15*")||cpuis("STM32L162?D")) group.word 0x50++0x1 elif (cpuis("STM32F2*")) elif (cpuis("STM32F4*")) endif width 0xB tree.end endif tree.end sif (!cpuis("STM32F411*")&&!cpuis("STM32F401*")) tree.open "BT (Basic Timers)" tree "TIM 6" base ad:0x40001000 width 11. group.word 0x00++0x01 line.word 0x00 "TIM6_CR1,Control Register 1" sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC") bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping" textline " " endif bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB") group.word 0x04++0x01 line.word 0x00 "TIM6_CR2,Control Register 2" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..." endif group.word 0x0C++0x01 line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM6_SR,Status Register" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update" wgroup.word 0x14++0x01 line.word 0x00 "TIM6_EGR,Event Generation Register" bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate" sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC") if ((per.l(ad:0x40001000)&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM6_CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM6_CNT,Counter" bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value" endif else group.word 0x24++0x01 line.word 0x00 "TIM6_CNT,Counter" endif group.word 0x28++0x01 line.word 0x00 "TIM6_PSC,Prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM6_ARR,Auto-Reload Register" width 0x0B tree.end sif !cpuis("STM32F410*") tree "TIM 7" base ad:0x40001400 width 11. group.word 0x00++0x01 line.word 0x00 "TIM7_CR1,Control Register 1" sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC") bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping" textline " " endif bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered" bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped" bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow" textline " " bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes" bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB") group.word 0x04++0x01 line.word 0x00 "TIM7_CR2,Control Register 2" bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..." endif group.word 0x0C++0x01 line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register" bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled" bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled" group.word 0x10++0x01 line.word 0x00 "TIM7_SR,Status Register" bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update" wgroup.word 0x14++0x01 line.word 0x00 "TIM7_EGR,Event Generation Register" bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate" sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC") if ((per.l(ad:0x40001400)&0x800)==0x000) group.long 0x24++0x03 line.long 0x00 "TIM7_CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value" else group.long 0x24++0x03 line.long 0x00 "TIM7_CNT,Counter" bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped" hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value" endif else group.word 0x24++0x01 line.word 0x00 "TIM7_CNT,Counter" endif group.word 0x28++0x01 line.word 0x00 "TIM7_PSC,Prescaler" group.word 0x2C++0x01 line.word 0x00 "TIM7_ARR,Auto-Reload Register" width 0x0B tree.end endif tree.end endif sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H") tree "LPTIM (Low-power Timer)" base ad:0x40002400 width 7. rgroup.long 0x00++0x03 line.long 0x00 "ISR,Interrupt And Status Register" bitfld.long 0x00 6. " DOWN ,Counter direction change up to down" "Not changed,Changed" bitfld.long 0x00 5. " UP ,Counter direction change down to up" "Not changed,Changed" bitfld.long 0x00 4. " ARROK ,Autoreload register update OK" "Not updated,Updated" bitfld.long 0x00 3. " CMPOK ,Compare register update OK" "Not updated,Updated" newline bitfld.long 0x00 2. " EXTTRIG ,External trigger edge even" "Not occurred,Occurred" bitfld.long 0x00 1. " ARRM ,Autoreload match" "Not matched,Matched" bitfld.long 0x00 0. " CMPM ,Compare match" "Not matched,Matched" wgroup.long 0x04++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 6. " DOWNCF ,Direction change to down clear flag" "No effect,Clear" bitfld.long 0x00 5. " UPCF ,Direction change to UP clear flag" "No effect,Clear" bitfld.long 0x00 4. " ARROKCF ,Autoreload register update OK clear flag" "No effect,Clear" bitfld.long 0x00 3. " CMPOKCF ,Compare register update OK clear flag" "No effect,Clear" newline bitfld.long 0x00 2. " EXTTRIGCF ,External trigger valid edge clear flag" "No effect,Clear" bitfld.long 0x00 1. " ARRMCF ,Autoreload match clear flag" "No effect,Clear" bitfld.long 0x00 0. " CMPMCF ,Compare match clear flag" "No effect,Clear" if ((per.l(ad:0x40002400+0x10)&0x01)==0x01) rgroup.long 0x08++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 6. " DOWNIE ,Direction change to down interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " UPIE ,Direction change to UP interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARROKIE ,Autoreload register update OK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CMPOKIE ,Compare register update OK interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " EXTTRIGIE ,External trigger valid edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ARRMIE ,Autoreload match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CMPMIE ,Compare match interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 6. " DOWNIE ,Direction change to down interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " UPIE ,Direction change to UP interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARROKIE ,Autoreload register update OK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CMPOKIE ,Compare register update OK interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " EXTTRIGIE ,External trigger valid edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ARRMIE ,Autoreload match interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CMPMIE ,Compare match interrupt enable" "Disabled,Enabled" endif if (((per.l(ad:0x40002400+0x10)&0x01)==0x01)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x1000000) rgroup.long 0x0C++0x03 line.long 0x00 "CFGR,Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" newline bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both" newline sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..." elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT" else bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..." endif newline sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F750*")||cpuis("STM32F76*")||cpuis("STM32F77*")) bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128" endif newline bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" elif (((per.l(ad:0x40002400+0x10)&0x01)==0x00)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "CFGR,Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" newline bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both" newline sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..." elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT" else bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..." endif newline sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")) bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128" endif newline bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Sub-mode 1,Sub-mode 2,Sub-mode 3,?..." bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" elif (((per.l(ad:0x40002400+0x10)&0x01)==0x01)&&(per.l(ad:0x40002400+0x0C)&0x1000000)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CFGR,Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" newline bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both" newline sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..." elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT" else bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..." endif newline sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")) bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128" endif newline bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Rising,Falling,Both,?..." bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" else group.long 0x0C++0x03 line.long 0x00 "CFGR,Configuration Register" bitfld.long 0x00 24. " ENC ,Encoder mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " COUNTMODE ,Counter mode enabled" "Disabled,Enabled" bitfld.long 0x00 22. " PRELOAD ,Registers update mode" "After APB,End of LPTIM" bitfld.long 0x00 21. " WAVPOL ,Waveform shape polarity" "Not inverted,Inverted" newline bitfld.long 0x00 20. " WAVE ,Waveform shape" "PWM / One Pulse,Set Once" bitfld.long 0x00 19. " TIMOUT ,Timeout enable" "Disabled,Enabled" bitfld.long 0x00 17.--18. " TRIGEN ,Trigger enable and polarity" "Software,Rising,Falling,Both" newline sif cpuis("STM32F410*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP,TIM1,TIM5,?..." elif (cpuis("STM32H743*")||cpuis("STM32H753*")) bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,COMP1_OUT,COMP2_OUT" else bitfld.long 0x00 13.--15. " TRIGSEL ,Trigger selector" "GPIO,RTC_ALARMA,RTC_ALARMB,RTC_TAMP1_OUT,RTC_TAMP2_OUT,RTC_TAMP3_OUT,?..." endif newline sif (cpuis("STM32H743*")||cpuis("STM32H753*")||cpuis("STM32F72*")||cpuis("STM32F73*")||cpuis("STM32F76*")||cpuis("STM32F77*")) bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else bitfld.long 0x00 9.--11. " PRESC ,Clock prescaler" "/1,/2,/6,/8,/16,/32,/64,/128" endif newline bitfld.long 0x00 6.--7. " TRGFLT ,Configurable digital filter for trigger" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 3.--4. " CKFLT ,Configurable digital filter for external clock" "Any change,2 clk periods,4 clk periods,8 clk periods" bitfld.long 0x00 1.--2. " CKPOL ,Clock polarity" "Rising,Falling,Both,?..." bitfld.long 0x00 0. " CKSEL ,Clock selector" "Internal,External" endif if ((per.l(ad:0x40002400+0x10)&0x01)==0x01) group.long 0x10++0x0B line.long 0x00 "CR,Control Register" bitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "Not started,Started" bitfld.long 0x00 1. " SNGSTRT ,LPTIM start in single mode" "Not started,Started" bitfld.long 0x00 0. " ENABLE ,LPTIM enable" "Disabled,Enabled" line.long 0x04 "CMP,Compare Register" hexmask.long.word 0x04 0.--15. 1. " CMP ,Compare value" line.long 0x08 "ARR,Autoreload Register" hexmask.long.word 0x08 0.--15. 1. " ARR ,Auto reload value" else group.long 0x10++0x03 line.long 0x00 "CR,Control Register" rbitfld.long 0x00 2. " CNTSTRT ,Timer start in continuous mode" "Not started,Started" rbitfld.long 0x00 1. " SNGSTRT ,LPTIM start in single mode" "Not started,Started" bitfld.long 0x00 0. " ENABLE ,LPTIM enable" "Disabled,Enabled" rgroup.long 0x14++0x07 line.long 0x00 "CMP,Compare Register" hexmask.long.word 0x00 0.--15. 1. " CMP ,Compare value" line.long 0x04 "ARR,Autoreload Register" hexmask.long.word 0x04 0.--15. 1. " ARR ,Auto reload value" endif rgroup.long 0x1C++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value" sif cpuis("STM32F410*") group.long 0x20++0x03 line.long 0x00 "OR,Option Register" bitfld.long 0x00 0.--1. " OR ,Low-power timer input 1 remap" "PB5/PC0,PA4,PB9,TIM6/DAC" elif (cpuis("STM32H743*")||cpuis("STM32H753*")) newline group.long 0x24++0x03 line.long 0x00 "CFGR2,Configuration Register 2" bitfld.long 0x00 4.--5. " IN2SEL ,LPTIM1 input 2 selection" "GPIO,COMP2_OUT,?..." bitfld.long 0x00 0.--1. " IN1SEL ,LPTIM1 input 1 selection" "GPIO,COMP1_OUT,?..." elif cpuis("STM32F413*")||cpuis("STM32F423?H") newline group.long 0x20++0x03 line.long 0x00 "OR,Option Register" bitfld.long 0x00 4. " TIM9_ITR1_RMP ,TIMER9 input trigger 1 remap" "TIM3 output trigger,LPTIMERS out channel" bitfld.long 0x00 3. " TIM5_ITR1_RMP ,TIMER5 intput trigger 1 remap" "TIM3 output trigger,LPTIMERS out channel" newline bitfld.long 0x00 2. " TIM1_ITR2_RMP ,TIMER1 input trigger 2 remap" "TIM3 output trigger,LPTIMERS out channel" bitfld.long 0x00 0.--1. " LPT_IN1_RMP ,LPTimer input trigger 2 remap" "PB5/PC0,PA4 direct,PB9 direct,LPTIMER out channel" endif width 0x0B tree.end endif tree "IWDG (Independent Watchdog)" base ad:0x40003000 width 11. wgroup.long 0x00++0x03 line.long 0x00 "IWDG_KR,Key Register" hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value" group.long 0x04++0x07 line.long 0x00 "IWDG_PR,Prescaler Register" bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256" line.long 0x04 "IWDG_RLR,Reload Register" hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value" rgroup.long 0x0C++0x03 line.long 0x00 "IWDG_SR,Status Register" sif ((cpu()=="STM32F050C4")||(cpu()=="STM32F050C6")||(cpu()=="STM32F050K4")||(cpu()=="STM32F050K6")||(cpu()=="STM32F051C4")||(cpu()=="STM32F051C6")||(cpu()=="STM32F051C8")||(cpu()=="STM32F051K4")||(cpu()=="STM32F051K6")||(cpu()=="STM32F051K8")||(cpu()=="STM32F051R4")||(cpu()=="STM32F051R6")||(cpu()=="STM32F051R8")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")) bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running" textline " " endif bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running" bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running" sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")) group.long 0x10++0x03 line.long 0x00 "IWDG_WINR,Window Register" hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value" endif width 0x0B tree.end tree "WWDG (Window Watchdog)" base ad:0x40002C00 width 10. group.long 0x00++0x0B line.long 0x00 "WWDG_CR,Control Register" bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter" line.long 0x04 "WWDG_CFR,Configuration Register" bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8" textline " " hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value" line.long 0x08 "WWDG_SR,Status Register" bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt" width 0x0B tree.end sif cpuis("STM32F423?H") tree "AES (Advanced Encryption Standard Hardware Accelerator)" base ad:0x50060000 width 12. if (((per.l(ad:0x50060000))&0x1)==0x0) group.long 0x00++0x03 line.long 0x00 "AES_CR,AES Control Register" bitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b" bitfld.long 0x00 13.--14. " GCMPH ,Used only for GCM_GMAC_CMAC algorithms and has no effect when other algorithms are selected" "Init,Header,Payload,Final" bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled" bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear" bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear" textline " " bitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&&GMAC,CMAC,?..." bitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key_der + Decrypt" bitfld.long 0x00 1.--2. " DATATYPE ,Data type selection (for data in and data out to/from the cryptographic block)" "32b-no swap,16b-swapped,8b-swapped,1b-swapped" bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "AES_CR,AES Control Register" rbitfld.long 0x00 18. " KEYSIZE ,Key size selection" "128b,256b" bitfld.long 0x00 13.--14. " GCMPH ,Used only for GCM_GMAC_CMAC algorithms and has no effect when other algorithms are selected" "Init,Header,Payload,Final" bitfld.long 0x00 12. " DMAOUTEN ,Enable DMA management of data output phase" "Disabled,Enabled" bitfld.long 0x00 11. " DMAINEN ,Enable DMA management of data input phase" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CCFIE ,CCF flag interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ERRC ,Error clear" "No effect,Clear" bitfld.long 0x00 7. " CCFC ,Computation complete flag clear" "No effect,Clear" textline " " rbitfld.long 0x00 5.--6. 16. " CHMOD ,AES chaining mode" "ECB,CBC,CTR,GCM&&GMAC,CMAC,?..." rbitfld.long 0x00 3.--4. " MODE ,AES operating mode" "Encryption,Key derivation,Decryption,Key_der + Decrypt" rbitfld.long 0x00 1.--2. " DATATYPE ,Data type selection (for data in and data out to/from the cryptographic block)" "32b-no swap,16b-swapped,8b-swapped,1b-swapped" bitfld.long 0x00 0. " EN ,AES enable" "Disabled,Enabled" endif rgroup.long 0x04++0x03 line.long 0x00 "AES_SR,AES Status Register" bitfld.long 0x00 3. " BUSY ,Busy flag" "Idle,Busy" bitfld.long 0x00 2. " WRERR ,Write error flag" "No error,Error" bitfld.long 0x00 1. " RDERR ,Read error flag" "No error,Error" bitfld.long 0x00 0. " CCF ,Computation complete flag" "Completed,Not completed" group.long 0x08++0x03 line.long 0x00 "AES_DINR,AES Data Input Register" rgroup.long 0x0C++0x03 line.long 0x00 "AES_DOUTR,AES Data Output Register" group.long 0x10++0x1F line.long 0x00 "AES_KEYR0,AES Key Register 0 [31:0]" line.long 0x04 "AES_KEYR1,AES Key Register 1 [63:32]" line.long 0x08 "AES_KEYR2,AES Key Register 2 [95:64]" line.long 0x0C "AES_KEYR3,AES Key Register 3 [127:96]" line.long 0x10 "AES_IVR0,AES Initialization Vector Register 0 [31:0]" line.long 0x14 "AES_IVR1,AES Initialization Vector Register 1 [63:32]" line.long 0x18 "AES_IVR2,AES Initialization Vector Register 2 [95:64]" line.long 0x1C "AES_IVR3,AES Initialization Vector Register 3 [127:96]" sif cpuis("STM32F423?H")||cpuis("STM32L4?6*")||cpuis("STM32L44*")||cpuis("STM32L451*")||cpuis("STM32L452*")||cpuis("STM32L462*") if (((per.l(ad:0x50060000))&0x40000)==0x40000) group.long 0x30++0x0F line.long 0x00 "AES_KEYR4,AES Key Register 4 [159:128]" line.long 0x04 "AES_KEYR5,AES Key Register 5 [191:160]" line.long 0x08 "AES_KEYR6,AES Key Register 6 [223:192]" line.long 0x0c "AES_KEYR7,AES Key Register 7 [255:224]" endif else if (((per.l(ad:0x50060000))&0x40000)==0x40000) group.long 0x30++0x0F line.long 0x00 "AES_IVR4,AES Initialization Vector Register 4 [159:128]" line.long 0x04 "AES_IVR5,AES Initialization Vector Register 5 [191:160]" line.long 0x08 "AES_IVR6,AES Initialization Vector Register 6 [223:192]" line.long 0x0c "AES_IVR7,AES Initialization Vector Register 7 [255:224]" endif endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x40++0x03 line.long 0x00 "AES_SUSP0R,AES Suspend Register" else wgroup.long 0x40++0x03 line.long 0x00 "AES_SUSP0R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x44++0x03 line.long 0x00 "AES_SUSP1R,AES Suspend Register" else wgroup.long 0x44++0x03 line.long 0x00 "AES_SUSP1R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x48++0x03 line.long 0x00 "AES_SUSP2R,AES Suspend Register" else wgroup.long 0x48++0x03 line.long 0x00 "AES_SUSP2R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x4C++0x03 line.long 0x00 "AES_SUSP3R,AES Suspend Register" else wgroup.long 0x4C++0x03 line.long 0x00 "AES_SUSP3R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x50++0x03 line.long 0x00 "AES_SUSP4R,AES Suspend Register" else wgroup.long 0x50++0x03 line.long 0x00 "AES_SUSP4R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x54++0x03 line.long 0x00 "AES_SUSP5R,AES Suspend Register" else wgroup.long 0x54++0x03 line.long 0x00 "AES_SUSP5R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x58++0x03 line.long 0x00 "AES_SUSP6R,AES Suspend Register" else wgroup.long 0x58++0x03 line.long 0x00 "AES_SUSP6R,AES Suspend Register" endif if (((per.l(ad:0x50060000))&0x1)==0x1) group.long 0x5C++0x03 line.long 0x00 "AES_SUSP7R,AES Suspend Register" else wgroup.long 0x5C++0x03 line.long 0x00 "AES_SUSP7R,AES Suspend Register" endif width 0x0B tree.end endif tree "RTC (Real-Time Clock)" base ad:0x40002800 width 14. if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)!=0x200000)) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC Time Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)==0x200000)) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC Time Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif ((per.l(ad:0x40002800)&0x300000)==0x100000) group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC Time Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" else group.long 0x00++0x3 line.long 0x00 "RTC_TR,RTC Time Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" endif if (((per.l(ad:0x40002800+0x04))&0x1F00)==(0x0100||0x0300||0x0500||0x0700||0x0800)) if (((per.l(ad:0x40002800+0x04))&0x30)==0x30) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04))&0x30)==0x00) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif elif (((per.l(ad:0x40002800+0x04))&0x1F00)==(0x1000||0x1200)) if (((per.l(ad:0x40002800+0x04))&0x30)==0x30) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04))&0x30)==0x00) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif elif (((per.l(ad:0x40002800+0x04))&0x1F00)==0x0200) if (((per.l(ad:0x40002800+0x04))&0x30)==0x30) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,-" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04))&0x30)==0x00) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,-" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,-" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif elif (((per.l(ad:0x40002800+0x04))&0x1F00)==(0x0400||0x0600||0x0900)) if (((per.l(ad:0x40002800+0x04))&0x30)==0x30) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04))&0x30)==0x00) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif elif (((per.l(ad:0x40002800+0x04))&0x1F00)==0x1100) if (((per.l(ad:0x40002800+0x04))&0x30)==0x30) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" elif (((per.l(ad:0x40002800+0x04))&0x30)==0x00) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif else if (((per.l(ad:0x40002800+0x04))&0x1000)==0x1000) group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" else group.long 0x04++0x3 line.long 0x00 "RTC_DR,RTC Date Register" bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12. "/,Month tens in BCD format" "0,1" bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 20.--23. "/,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" endif endif group.long 0x08++0xF line.long 0x00 "RTC_CR,RTC Control Register" sif (cpuis("STM32F7*")||cpuis("STM32H753*")||cpuis("STM32H743*")) bitfld.long 0x00 24. " ITSE ,Timestamp on internal event enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup" bitfld.long 0x00 20. " POL ,Output polarity" "High,Low" bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz" textline " " bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed" bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted" bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added" bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled" bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled" bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled" sif (!cpuis("STM32F76*")&&!cpuis("STM32F77*")&&!cpuis("STM32H753*")&&!cpuis("STM32H743*")) bitfld.long 0x00 7. " DCE ,Digital calibration enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 6. " FMT ,Hour format" "24 hours,AM/PM" bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers " "Disabled,Enabled" bitfld.long 0x00 4. " REFCKON ,Reference clock detection enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge" textline " " bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,Ck_spre,Ck_spre,Ck_spre/WUT+=0x10000,Ck_spre/WUT+=0x10000" line.long 0x04 "RTC_ISR,RTC Initialization And Status Register" sif (cpuis("STM32F7*")||cpuis("STM32H753*")||cpuis("STM32H743*")) bitfld.long 0x04 17. " ITSF ,Internal tTime-stamp flag" "Not occurred,Occurred" textline " " endif rbitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected" sif cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H753*")||cpuis("STM32H743*") bitfld.long 0x04 15. " TAMP3F ,TAMPER3 detection flag" "Not detected,Detected" bitfld.long 0x04 14. " TAMP2F ,TAMPER2 detection flag" "Not detected,Detected" elif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x04 14. " TAMP2F ,TAMPER2 detection flag" "Not detected,Detected" endif textline " " bitfld.long 0x04 13. " TAMP1F ,Tamper detection flag" "Not detected,Detected" bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "No overflow,Overflow" textline " " bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred" bitfld.long 0x04 10. " WUTF ,Wakeup timer flag" "Not occurred,Occurred" bitfld.long 0x04 9. " ALRBF ,Alarm B flag" "Not occurred,Occurred" bitfld.long 0x04 8. " ALRAF ,Alarm A flag" "Not occurred,Occurred" textline " " bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Initialization" rbitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed" bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized" rbitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized" textline " " sif (cpuis("STM32F446*")||cpuis("STM32F401?D")||cpuis("STM32F401?E")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")||cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H753*")||cpuis("STM32H743*")) rbitfld.long 0x04 3. " SHPF ,Shift operation pending" "Not pending,Pending" else bitfld.long 0x04 3. " SHPF ,Shift operation pending" "Not pending,Pending" endif rbitfld.long 0x04 2. " WUTWF ,Wakeup timer write flag" "Not allowed,Allowed" rbitfld.long 0x04 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed" rbitfld.long 0x04 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed" line.long 0x08 "RTC_PRER,RTC Prescaler Register" hexmask.long.byte 0x08 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor" hexmask.long.word 0x08 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor" line.long 0xC "RTC_WUTR,RTC Wakeup Timer Register" hexmask.long.word 0xC 0.--15. 1. " WUT ,Wakeup auto-reload value bits" sif (!cpuis("STM32F7*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32H753*")&&!cpuis("STM32H743*")) if (((per.l(ad:0x40002800+0x0C))&0x40)==0x40) if ((per.l((ad:0x40002800)+0x18)&0x80)==0x0) group.long 0x18++0x3 line.long 0x00 "RTC_CALIBR,RTC Calibration Register" bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative" bitfld.long 0x00 0.--4. " DC ,Digital calibration" "+0 ppm,+4 ppm,+8 ppm,+12 ppm,+16 ppm,+20 ppm,+24 ppm,+28 ppm,+32 ppm,+36 ppm,+40 ppm,+44 ppm,+48 ppm,+52 ppm,+56 ppm,+60 ppm,+64 ppm,+68 ppm,+72 ppm,+76 ppm,+80 ppm,+84 ppm,+88 ppm,+92 ppm,+96 ppm,+100 ppm,+104 ppm,+108 ppm,+112 ppm,+116 ppm,+120 ppm,+126 ppm" else group.long 0x18++0x3 line.long 0x00 "RTC_CALIBR,RTC Calibration Register" bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative" bitfld.long 0x00 0.--4. " DC ,Digital calibration" "-0 ppm,-2 ppm,-4 ppm,-6 ppm,-8 ppm,-10 ppm,-12 ppm,-14 ppm,-16 ppm,-18 ppm,-20 ppm,-22 ppm,-24 ppm,-26 ppm,-28 ppm,-30 ppm,-32 ppm,-34 ppm,-36 ppm,-38 ppm,-40 ppm,-42 ppm,-44 ppm,-46 ppm,-48 ppm,-50 ppm,-52 ppm,-54 ppm,-56 ppm,-58 ppm,-60 ppm,-63 ppm" endif else if ((per.l((ad:0x40002800)+0x18)&0x80)==0x0) rgroup.long 0x18++0x3 line.long 0x00 "RTC_CALIBR,RTC Calibration Register" bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative" bitfld.long 0x00 0.--4. " DC ,Digital calibration" "+0 ppm,+4 ppm,+8 ppm,+12 ppm,+16 ppm,+20 ppm,+24 ppm,+28 ppm,+32 ppm,+36 ppm,+40 ppm,+44 ppm,+48 ppm,+52 ppm,+56 ppm,+60 ppm,+64 ppm,+68 ppm,+72 ppm,+76 ppm,+80 ppm,+84 ppm,+88 ppm,+92 ppm,+96 ppm,+100 ppm,+104 ppm,+108 ppm,+112 ppm,+116 ppm,+120 ppm,+126 ppm" else rgroup.long 0x18++0x3 line.long 0x00 "RTC_CALIBR,RTC Calibration Register" bitfld.long 0x00 7. " DCS ,Digital calibration sign" "Positive,Negative" bitfld.long 0x00 0.--4. " DC ,Digital calibration" "-0 ppm,-2 ppm,-4 ppm,-6 ppm,-8 ppm,-10 ppm,-12 ppm,-14 ppm,-16 ppm,-18 ppm,-20 ppm,-22 ppm,-24 ppm,-26 ppm,-28 ppm,-30 ppm,-32 ppm,-34 ppm,-36 ppm,-38 ppm,-40 ppm,-42 ppm,-44 ppm,-46 ppm,-48 ppm,-50 ppm,-52 ppm,-54 ppm,-56 ppm,-58 ppm,-60 ppm,-63 ppm" endif endif endif if (((per.l(ad:0x40002800+0x0C))&0x41)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40) if (((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000) if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif elif (((per.l(ad:0x40002800+0x0C))&0x41)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00) if (((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000) if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif elif (((per.l(ad:0x40002800+0x08))&0x40)==0x40) if (((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x100000) if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif else if (((per.l(ad:0x40002800+0x1C))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x300000)==0x200000) if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x30000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x1C))&0x30000000)==0x00000000) group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x1C++0x03 line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif endif if (((per.l(ad:0x40002800+0x0C))&0x42)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x40) if (((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x20))&0x300000)==0x100000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x300000)==0x100000) if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif elif (((per.l(ad:0x40002800+0x0C))&0x42)==0x00)&&(((per.l(ad:0x40002800+0x08))&0x40)==0x00) if (((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x20))&0x300000)==0x200000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x300000)==0x200000) if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else rgroup.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif elif (((per.l(ad:0x40002800+0x08))&0x40)==0x40) if (((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x20))&0x300000)==0x100000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x300000)==0x100000) if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif else if (((per.l(ad:0x40002800+0x20))&0x40000000)==0x40000000) if (((per.l(ad:0x40002800+0x20))&0x300000)==0x200000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 24.--27. " DAY ,Day of the week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x300000)==0x200000) if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif else if (((per.l(ad:0x40002800+0x20))&0x30000000)==0x30000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" elif (((per.l(ad:0x40002800+0x20))&0x30000000)==0x00000000) group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" else group.long 0x20++0x03 line.long 0x00 "RTC_ALRMBR,RTC Alarm B Register" bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" textline " " bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day" textline " " bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked" bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked" bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked" endif endif endif endif wgroup.long 0x24++0x3 line.long 0x00 "RTC_WPR,RTC Write Protection Register" hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key" rgroup.long 0x28++0x03 line.long 0x00 "RTC_SSR,RTC Sub Second Register" hexmask.long.word 0x00 0.--15. 1. " SS , Sub second value" sif (cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H753*")||cpuis("STM32H743*")) wgroup.long 0x2C++0x03 line.long 0x00 "RTC_SHIFTR,RTC Shift Control Register" bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Add" hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second" else group.long 0x2C++0x03 line.long 0x00 "RTC_SHIFTR,RTC Shift Control Register" bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Added" hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second" endif if ((per.l((ad:0x40002800)+0xC)&0x800)==0x0) hgroup.long 0x30++0x03 hide.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register" hgroup.long 0x34++0x03 hide.long 0x00 "RTC_TSDR,RTC Time Stamp Date Register" hgroup.long 0x38++0x03 hide.long 0x00 "RTC_TSSSR,RTC Time Stamp Sub Second Register" hgroup.long 0x3C++0x03 hide.long 0x00 "RTC_CALR,RTC Calibration Register" elif (((per.l((ad:0x40002800)+0xC)&0x800)==0x800)&&((per.l(ad:0x40002800+0x8)&0x40)==0x0)) rgroup.long 0x30++0xF line.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register" sif cpuis("STM32H753*")||cpuis("STM32H743*") bitfld.long 0x00 22. " PM , AM/PM notation" "AM,PM" textline " " endif bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" line.long 0x04 "RTC_TSDR,RTC Time Stamp Date Register" bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" line.long 0x08 "RTC_TSSSR,RTC Time Stamp Sub Second Register" hexmask.long.word 0x08 0.--15. 1. " SS ,Sub second value" line.long 0x0C "RTC_CALR,RTC Calibration Register" bitfld.long 0x0C 15. " CALP ,Increase frequency of RTC" "Not increased,Increased" bitfld.long 0x0C 14. " CALW8 ,Use an 8-second calibration cycle period" "Not used,Used" textline " " bitfld.long 0x0C 13. " CALW16 ,Use a 16-second calibration cycle period" "Not used,Used" hexmask.long.word 0x0C 0.--8. 1. " CALM ,Calibration minus" else rgroup.long 0x30++0xF line.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register" sif cpuis("STM32H753*")||cpuis("STM32H743*") bitfld.long 0x00 22. " PM , AM/PM notation" "AM,PM" textline " " endif bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-" bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM" line.long 0x04 "RTC_TSDR,RTC Time Stamp Date Register" bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday" bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3" bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1" bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-" line.long 0x08 "RTC_TSSSR,RTC Time Stamp Sub Second Register" hexmask.long.word 0x08 0.--15. 1. " SS ,Sub second value" line.long 0x0C "RTC_CALR,RTC Calibration Register" bitfld.long 0x0C 15. " CALP ,Increase frequency of RTC" "Not increased,Increased" bitfld.long 0x0C 14. " CALW8 ,Use an 8-second calibration cycle period" "Not used,Used" textline " " bitfld.long 0x0C 13. " CALW16 ,Use a 16-second calibration cycle period" "Not used,Used" hexmask.long.word 0x0C 0.--8. 1. " CALM ,Calibration minus" endif textline "" sif (cpuis("STM32F7*")||cpuis("STM32H753*")||cpuis("STM32H743*")) if ((per.l(ad:0x40002800+0x40)&0x1800)!=0x0) group.long 0x40++0x3 line.long 0x00 "RTC_TAMPCR,RTC Tamper Configuration Register" bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked" bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "No,Yes" textline " " bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" textline " " bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "No,Yes" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "No,Yes" textline " " bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1Cycle,2Cycles,4Cycles,8Cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "OnEdge,2Samples,4Samples,8Samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Low,High" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Low,High" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High" textline " " bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 detection enable" "Disabled,Enabled" else group.long 0x40++0x3 line.long 0x00 "RTC_TAMPCR,RTC Tamper Configuration Register" bitfld.long 0x00 24. " TAMP3MF ,Tamper 3 mask flag" "Not masked,Masked" bitfld.long 0x00 23. " TAMP3NOERASE ,Tamper 3 no erase" "No,Yes" textline " " bitfld.long 0x00 22. " TAMP3IE ,Tamper 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " TAMP2MF ,Tamper 2 mask flag" "Not masked,Masked" textline " " bitfld.long 0x00 20. " TAMP2NOERASE ,Tamper 2 no erase" "No,Yes" bitfld.long 0x00 19. " TAMP2IE ,Tamper 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TAMP1MF ,Tamper 1 mask flag" "Not masked,Masked" bitfld.long 0x00 17. " TAMP1NOERASE ,Tamper 1 no erase" "No,Yes" textline " " bitfld.long 0x00 16. " TAMP1IE ,Tamper 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1Cycle,2Cycles,4Cycles,8Cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "OnEdge,2Samples,4Samples,8Samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Rising,Falling" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Rising,Falling" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Rising,Falling" textline " " bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 detection enable" "Disabled,Enabled" endif elif (cpuis("STM32F469*")||cpuis("STM32F479*")) if ((per.l(ad:0x40002800+0x40)&0x1800)!=0x0) group.long 0x40++0x3 line.long 0x00 "RTC_TAFCR,RTC Tamper And Alternate Function Configuration Register" bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby,Push-pull" bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1" textline " " bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby,Push-pull" bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1" textline " " bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby,Push-pull" bitfld.long 0x00 18. " PC13VALUE ,PC13 value" "0,1" textline " " bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1 cycle,2 cycles,4 cycles,8 cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge,2 samples,4 samples,8 samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Low,High" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Low,High" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High" textline " " bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 detection enable" "Disabled,Enabled" else group.long 0x40++0x3 line.long 0x00 "RTC_TAFCR,RTC Tamper And Alternate Function Configuration Register" bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby,Push-pull" bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1" textline " " bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby,Push-pull" bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1" textline " " bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby,Push-pull" bitfld.long 0x00 18. " PC13VALUE ,PC13 value" "0,1" textline " " bitfld.long 0x00 15. " TAMPPUDIS ,RTC_TAMPx pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1 cycle,2 cycles,4 cycles,8 cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,RTC_TAMPx filter count" "On edge,2 samples,4 samples,8 samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "/32768,/16384,/8192,/4096,/2048,/1024,/512,/256" bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Not saved,Saved" textline " " bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Rising,Falling" bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP2 input" "Rising,Falling" bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 detection enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Rising,Falling" textline " " bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 detection enable" "Disabled,Enabled" endif else if ((per.l(ad:0x40002800+0x40)&0x1800)!=0x0) group.long 0x40++0x3 line.long 0x00 "RTC_TAFCR,RTC Tamper And Alternate Function Configuration Register" bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Open-drain,Push-pull" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 17. " TSINSEL ,TIMESTAMP mapping" "RTC_AF1 TIMESTAMP,?..." textline " " bitfld.long 0x00 16. " TAMP1INSEL ,TAMPER1 mapping" "RTC_AF1 TAMPER,?..." else bitfld.long 0x00 17. " TSINSEL ,TIMESTAMP mapping" "RTC_AF1 TIMESTAMP,RTC_AF2 TIMESTAMP" textline " " bitfld.long 0x00 16. " TAMP1INSEL ,TAMPER1 mapping" "RTC_AF1 TAMPER,RTC_AF2 TAMPER" endif bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1Cycle,2Cycles,4Cycles,8Cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,Number of consecutive samples at the specified level necessary to activate" "OnEdge,2Samples,4Samples,8Samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency RTCCLK" "/32786,/16384,/8192,/4096,/2048,/512,/256,?..." bitfld.long 0x00 7. " TAMPTS ,Timestamp on tamper detection event" "No save,Save" textline " " sif (!cpuis("STM32F401*"))&&(!cpuis("STM32F411*")&&!cpuis("STM32F412*")) bitfld.long 0x00 4. " TAMP2TRG ,Tamper 2 detection trigger" "Low,High" bitfld.long 0x00 3. " TAMP2E ,Tamper 2 detection enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Tamper 1 detection trigger" "Low,High" textline " " bitfld.long 0x00 0. " TAMP1E ,Tamper 1 detection enable" "Disabled,Enabled" else group.long 0x40++0x3 line.long 0x00 "RTC_TAFCR,RTC Tamper And Alternate Function Configuration Register" bitfld.long 0x00 18. " ALARMOUTTYPE ,AFO_ALARM output type" "Push-pull,Open-drain" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 17. " TSINSEL ,TIMESTAMP mapping" "RTC_AF1 TIMESTAMP,?..." textline " " bitfld.long 0x00 16. " TAMP1INSEL ,TAMPER1 mapping" "RTC_AF1 TAMPER,?..." else bitfld.long 0x00 17. " TSINSEL ,TIMESTAMP mapping" "RTC_AF1 TIMESTAMP,RTC_AF2 TIMESTAMP" textline " " bitfld.long 0x00 16. " TAMP1INSEL ,TAMPER1 mapping" "RTC_AF1 TAMPER,RTC_AF2 TAMPER" endif bitfld.long 0x00 15. " TAMPPUDIS ,TAMPER pull-up disable" "No,Yes" textline " " bitfld.long 0x00 13.--14. " TAMPPRCH , Tamper precharge duration" "1Cycle,2Cycles,4Cycles,8Cycles" bitfld.long 0x00 11.--12. " TAMPFLT ,Number of consecutive samples at the specified level necessary to activate" "OnEdge,2Samples,4Samples,8Samples" textline " " bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency RTCCLK" "/32786,/16384,/8192,/4096,/2048,/512,/256,?..." bitfld.long 0x00 7. " TAMPTS ,Timestamp on tamper detection event" "Not Save,Save" textline " " sif (!cpuis("STM32F401*"))&&(!cpuis("STM32F411*"))&&(!cpuis("STM32F412*"))&&(!cpuis("STM32F413*"))&&(!cpuis("STM32F423?H")) bitfld.long 0x00 4. " TAMP2TRG ,Active level for tamper 2 edge" "Rising,Falling" bitfld.long 0x00 3. " TAMP2E ,Tamper 2 detection enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TAMP1TRG ,Tamper 1 detection trigger" "Rising,Falling" textline " " bitfld.long 0x00 0. " TAMP1E ,Tamper 1 detection enable" "Disabled,Enabled" endif endif group.long 0x44++0x07 sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32H753*")||cpuis("STM32H743*")) line.long 0x00 "RTC_ALRMASSR,RTC Alarm A Sub Second Register" bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "SS[14:0],SS[14:1],SS[14:2],SS[14:3],SS[14:4],SS[14:5],SS[14:6],SS[14:7],SS[14:8],SS[14:9],SS[14:10],SS[14:11],SS[14:12],SS[14:13],SS[14],No mask" textline " " hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" line.long 0x04 "RTC_ALRMBSSR,RTC Alarm B Sub Second Register" bitfld.long 0x04 24.--27. " MASKSS ,Mask the most-significant bits" "SS[14:0],SS[14:1],SS[14:2],SS[14:3],SS[14:4],SS[14:5],SS[14:6],SS[14:7],SS[14:8],SS[14:9],SS[14:10],SS[14:11],SS[14:12],SS[14:13],SS[14],No mask" textline " " hexmask.long.word 0x04 0.--14. 1. " SS ,Sub seconds value" else line.long 0x00 "RTC_ALRMASSR,RTC Alarm A Sub Second Register" bitfld.long 0x00 27. " MASKSS ,Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x00 26. ",Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x00 25. ",Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x00 24. ",Mask the most-significant bits starting at this bit" "0,1" textline " " hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value" line.long 0x04 "RTC_ALRMBSSR,RTC Alarm B Sub Second Register" bitfld.long 0x04 27. " MASKSS ,Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x04 26. ",Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x04 25. ",Mask the most-significant bits starting at this bit" "0,1" bitfld.long 0x04 24. ",Mask the most-significant bits starting at this bit" "0,1" textline " " hexmask.long.word 0x04 0.--14. 1. " SS ,Sub seconds value" endif textline " " sif (cpuis("STM32F7*")) group.long 0x4C++0x03 line.long 0x00 "RTC_OR,RTC Option Register" bitfld.long 0x00 3. " RTC_ALARM_TYPE ,RTC_ALARM on PC13 output type" "Open-drain,Push-pull" bitfld.long 0x00 1.--2. " TSINSEL ,TIMESTAMP mapping" "PC13,PI8,PC1,PC1" elif cpuis("STM32H753*")||cpuis("STM32H743*") group.long 0x4C++0x03 line.long 0x00 "RTC_OR,RTC Option Register" bitfld.long 0x00 1. " RTC_OUT_RMP ,RTC_OUT remap" "PC13,PB2/PC13" bitfld.long 0x00 0. " RTC_ALARM_TYPE ,RTC_ALARM output type on PC13" "Open-drain,Push-pull" endif width 12. tree "RTC backup registers" sif (cpuis("STM32F7*")||cpuis("STM32H753*")||cpuis("STM32H743*")) group.long 0x50++0x03 line.long 0x00 "RTC_BKP0R,RTC Backup Register 0" group.long 0x54++0x03 line.long 0x00 "RTC_BKP1R,RTC Backup Register 1" group.long 0x58++0x03 line.long 0x00 "RTC_BKP2R,RTC Backup Register 2" group.long 0x5C++0x03 line.long 0x00 "RTC_BKP3R,RTC Backup Register 3" group.long 0x60++0x03 line.long 0x00 "RTC_BKP4R,RTC Backup Register 4" group.long 0x64++0x03 line.long 0x00 "RTC_BKP5R,RTC Backup Register 5" group.long 0x68++0x03 line.long 0x00 "RTC_BKP6R,RTC Backup Register 6" group.long 0x6C++0x03 line.long 0x00 "RTC_BKP7R,RTC Backup Register 7" group.long 0x70++0x03 line.long 0x00 "RTC_BKP8R,RTC Backup Register 8" group.long 0x74++0x03 line.long 0x00 "RTC_BKP9R,RTC Backup Register 9" group.long 0x78++0x03 line.long 0x00 "RTC_BKP10R,RTC Backup Register 10" group.long 0x7C++0x03 line.long 0x00 "RTC_BKP11R,RTC Backup Register 11" group.long 0x80++0x03 line.long 0x00 "RTC_BKP12R,RTC Backup Register 12" group.long 0x84++0x03 line.long 0x00 "RTC_BKP13R,RTC Backup Register 13" group.long 0x88++0x03 line.long 0x00 "RTC_BKP14R,RTC Backup Register 14" group.long 0x8C++0x03 line.long 0x00 "RTC_BKP15R,RTC Backup Register 15" group.long 0x90++0x03 line.long 0x00 "RTC_BKP16R,RTC Backup Register 16" group.long 0x94++0x03 line.long 0x00 "RTC_BKP17R,RTC Backup Register 17" group.long 0x98++0x03 line.long 0x00 "RTC_BKP18R,RTC Backup Register 18" group.long 0x9C++0x03 line.long 0x00 "RTC_BKP19R,RTC Backup Register 19" group.long 0xA0++0x03 line.long 0x00 "RTC_BKP20R,RTC Backup Register 20" group.long 0xA4++0x03 line.long 0x00 "RTC_BKP21R,RTC Backup Register 21" group.long 0xA8++0x03 line.long 0x00 "RTC_BKP22R,RTC Backup Register 22" group.long 0xAC++0x03 line.long 0x00 "RTC_BKP23R,RTC Backup Register 23" group.long 0xB0++0x03 line.long 0x00 "RTC_BKP24R,RTC Backup Register 24" group.long 0xB4++0x03 line.long 0x00 "RTC_BKP25R,RTC Backup Register 25" group.long 0xB8++0x03 line.long 0x00 "RTC_BKP26R,RTC Backup Register 26" group.long 0xBC++0x03 line.long 0x00 "RTC_BKP27R,RTC Backup Register 27" group.long 0xC0++0x03 line.long 0x00 "RTC_BKP28R,RTC Backup Register 28" group.long 0xC4++0x03 line.long 0x00 "RTC_BKP29R,RTC Backup Register 29" group.long 0xC8++0x03 line.long 0x00 "RTC_BKP30R,RTC Backup Register 30" group.long 0xCC++0x03 line.long 0x00 "RTC_BKP31R,RTC Backup Register 31" elif (cpuis("STM32F469*")||cpuis("STM32F479*")) group.long 0x50++0x03 line.long 0x00 "RTC_BKP0R,RTC Backup Register 0" group.long 0x54++0x03 line.long 0x00 "RTC_BKP1R,RTC Backup Register 1" group.long 0x58++0x03 line.long 0x00 "RTC_BKP2R,RTC Backup Register 2" group.long 0x5C++0x03 line.long 0x00 "RTC_BKP3R,RTC Backup Register 3" group.long 0x60++0x03 line.long 0x00 "RTC_BKP4R,RTC Backup Register 4" group.long 0x64++0x03 line.long 0x00 "RTC_BKP5R,RTC Backup Register 5" group.long 0x68++0x03 line.long 0x00 "RTC_BKP6R,RTC Backup Register 6" group.long 0x6C++0x03 line.long 0x00 "RTC_BKP7R,RTC Backup Register 7" group.long 0x70++0x03 line.long 0x00 "RTC_BKP8R,RTC Backup Register 8" group.long 0x74++0x03 line.long 0x00 "RTC_BKP9R,RTC Backup Register 9" group.long 0x78++0x03 line.long 0x00 "RTC_BKP10R,RTC Backup Register 10" group.long 0x7C++0x03 line.long 0x00 "RTC_BKP11R,RTC Backup Register 11" group.long 0x80++0x03 line.long 0x00 "RTC_BKP12R,RTC Backup Register 12" group.long 0x84++0x03 line.long 0x00 "RTC_BKP13R,RTC Backup Register 13" group.long 0x88++0x03 line.long 0x00 "RTC_BKP14R,RTC Backup Register 14" group.long 0x8C++0x03 line.long 0x00 "RTC_BKP15R,RTC Backup Register 15" else group.long 0x50++0x4F line.long 0x0 "RTC_BKP0R,RTC Backup Register 0" line.long 0x4 "RTC_BKP1R,RTC Backup Register 1" line.long 0x8 "RTC_BKP2R,RTC Backup Register 2" line.long 0xC "RTC_BKP3R,RTC Backup Register 3" line.long 0x10 "RTC_BKP4R,RTC Backup Register 4" line.long 0x14 "RTC_BKP5R,RTC Backup Register 5" line.long 0x18 "RTC_BKP6R,RTC Backup Register 6" line.long 0x1C "RTC_BKP7R,RTC Backup Register 7" line.long 0x20 "RTC_BKP8R,RTC Backup Register 8" line.long 0x24 "RTC_BKP9R,RTC Backup Register 9" line.long 0x28 "RTC_BKP10R,RTC Backup Register 10" line.long 0x2C "RTC_BKP11R,RTC Backup Register 11" line.long 0x30 "RTC_BKP12R,RTC Backup Register 12" line.long 0x34 "RTC_BKP13R,RTC Backup Register 13" line.long 0x38 "RTC_BKP14R,RTC Backup Register 14" line.long 0x3C "RTC_BKP15R,RTC Backup Register 15" line.long 0x40 "RTC_BKP16R,RTC Backup Register 16" line.long 0x44 "RTC_BKP17R,RTC Backup Register 17" line.long 0x48 "RTC_BKP18R,RTC Backup Register 18" line.long 0x4C "RTC_BKP19R,RTC Backup Register 19" endif tree.end width 0x0B tree.end sif cpuis("STM32F410*")&&!cpuis("STM32F410T*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") tree.open "FMPI2C (Fast-Mode Plus Inter-Integrated Circuit)" tree "I2CFMP 1" base ad:0x40006000 width 17. if (((per.l(ad:0x40006000))&0x100001)==0x100001) group.long 0x00++0x03 line.long 0x00 "FMPI2C_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter disable" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,Up to 1*TI2CCLK,Up to 2*TI2CCLK,Up to 3*TI2CCLK,Up to 4*TI2CCLK,Up to 5*TI2CCLK,Up to 6*TI2CCLK,Up to 7*TI2CCLK,Up to 8*TI2CCLK,Up to 9*TI2CCLK,Up to 10*TI2CCLK,Up to 11*TI2CCLK,Up to 12*TI2CCLK,Up to 13*TI2CCLK,Up to 14*TI2CCLK,Up to 15*TI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXIE , RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif (((per.l(ad:0x40006000))&0x100001)==0x000001) group.long 0x00++0x03 line.long 0x00 "FMPI2C_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter disable" "No,Yes" rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,Up to 1*TI2CCLK,Up to 2*TI2CCLK,Up to 3*TI2CCLK,Up to 4*TI2CCLK,Up to 5*TI2CCLK,Up to 6*TI2CCLK,Up to 7*TI2CCLK,Up to 8*TI2CCLK,Up to 9*TI2CCLK,Up to 10*TI2CCLK,Up to 11*TI2CCLK,Up to 12*TI2CCLK,Up to 13*TI2CCLK,Up to 14*TI2CCLK,Up to 15*TI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXIE , RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" elif (((per.l(ad:0x40006000))&0x100001)==0x100000) group.long 0x00++0x03 line.long 0x00 "FMPI2C_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Not supported,Supported" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter disable" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,Up to 1*TI2CCLK,Up to 2*TI2CCLK,Up to 3*TI2CCLK,Up to 4*TI2CCLK,Up to 5*TI2CCLK,Up to 6*TI2CCLK,Up to 7*TI2CCLK,Up to 8*TI2CCLK,Up to 9*TI2CCLK,Up to 10*TI2CCLK,Up to 11*TI2CCLK,Up to 12*TI2CCLK,Up to 13*TI2CCLK,Up to 14*TI2CCLK,Up to 15*TI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXIE , RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "FMPI2C_CR1,Control Register 1" bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled" bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled" bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled" bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled" bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes" bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled" bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled" bitfld.long 0x00 12. " ANFOFF ,Analog noise filter disable" "No,Yes" bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,Up to 1*TI2CCLK,Up to 2*TI2CCLK,Up to 3*TI2CCLK,Up to 4*TI2CCLK,Up to 5*TI2CCLK,Up to 6*TI2CCLK,Up to 7*TI2CCLK,Up to 8*TI2CCLK,Up to 9*TI2CCLK,Up to 10*TI2CCLK,Up to 11*TI2CCLK,Up to 12*TI2CCLK,Up to 13*TI2CCLK,Up to 14*TI2CCLK,Up to 15*TI2CCLK" bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RXIE , RX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled" endif if (((per.l(ad:0x40006000+0x08))&0x8000)==0x00)&&(((per.l(ad:0x40006000+0x0C))&0x8000)==0x00) if (((per.l(ad:0x40006000+0x04))&0x1000800)==0x1000800) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address" elif (((per.l(ad:0x40006000+0x04))&0x1000800)==0x1000000) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" textline " " bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.byte 0x00 1.--7. 0x02 " SADD ,Slave address" elif (((per.l(ad:0x40006000+0x04))&0x2800)==0x2800) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address" elif (((per.l(ad:0x40006000+0x04))&0x2800)==0x2000) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.byte 0x00 1.--7. 0x02 " SADD ,Slave address" elif (((per.l(ad:0x40006000+0x04))&0x2800)==0x0800) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.word 0x00 0.--9. 0x01 " SADD ,Slave address" else group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software,Automatic" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" textline " " bitfld.long 0x00 14. " STOP ,Stop generation" "Not generated,Generated" bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "Complete,Short" bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit" textline " " bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read" hexmask.long.byte 0x00 1.--7. 0x02 " SADD ,Slave address" endif else if (((per.l(ad:0x40006000))&0x10000)==0x10000)&&(((per.l(ad:0x40006000+0x04))&0x1000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK,NACK" textline " " bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" elif (((per.l(ad:0x40006000))&0x10000)==0x00000)&&(((per.l(ad:0x40006000+0x04))&0x1000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK,NACK" bitfld.long 0x00 13. " START ,Start generation" "Not generated,Generated" else group.long 0x04++0x03 line.long 0x00 "FMPI2C_CR2,Control Register 2" bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed" hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes to be transmitted/received" bitfld.long 0x00 15. " NACK ,NACK generation" "ACK,NACK" endif endif if (((per.l(ad:0x40006000+0x08))&0x8400)==0x8400) group.long 0x08++0x03 line.long 0x00 "FMPI2C_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit" hexmask.long.word 0x00 0.--9. 0x1 " OA1 ,Interface address" elif (((per.l(ad:0x40006000+0x08))&0x8400)==0x8000) group.long 0x08++0x03 line.long 0x00 "FMPI2C_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit" hexmask.long.byte 0x00 1.--7. 0x2 " OA1 ,Interface address" elif (((per.l(ad:0x40006000+0x08))&0x8400)==0x0400) group.long 0x08++0x03 line.long 0x00 "FMPI2C_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit" hexmask.long.word 0x00 0.--9. 0x1 " OA1 ,Interface address" else group.long 0x08++0x03 line.long 0x00 "FMPI2C_OAR1,Own Address 1 Register" bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled" bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit" hexmask.long.byte 0x00 1.--7. 0x2 " OA1 ,Interface address" endif if (((per.l(ad:0x40006000+0x0C))&0x8000)==0x8000) group.long 0x0C++0x03 line.long 0x00 "FMPI2C_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "Not masked,OA2[1],OA2[2:1],OA2[3:1],OA2[4:1],OA2[5:1],OA2[6:1],OA2[7:1]" hexmask.long.byte 0x00 1.--7. 0x02 " OA2 ,Interface address" else group.long 0x0C++0x03 line.long 0x00 "FMPI2C_OAR2,Own Address 2 Register" bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "Not masked,OA2[1],OA2[2:1],OA2[3:1],OA2[4:1],OA2[5:1],OA2[6:1],OA2[7:1]" hexmask.long.byte 0x00 1.--7. 0x02 " OA2 ,Interface address" endif if (((per.l(ad:0x40006000))&0x01)==0x01) if (((per.l(ad:0x40006000+0x08))&0x8000)==0x00)&&(((per.l(ad:0x40006000+0x0C))&0x8000)==0x00) rgroup.long 0x10++0x03 line.long 0x00 "FMPI2C_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH , SCL high period" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL , SCL low period" else rgroup.long 0x10++0x03 line.long 0x00 "FMPI2C_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40006000+0x08))&0x8000)==0x00)&&(((per.l(ad:0x40006000+0x0C))&0x8000)==0x00) group.long 0x10++0x03 line.long 0x00 "FMPI2C_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " SCLH , SCL high period" textline " " hexmask.long.byte 0x00 0.--7. 1. " SCLL , SCL low period" else group.long 0x10++0x03 line.long 0x00 "FMPI2C_TIMINGR,Timing Register" bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0x40006000+0x14))&0x8000)==0x8000) group.long 0x14++0x03 line.long 0x00 "FMPI2C_TIMEOUTR,Timeout register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeoout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A" else group.long 0x14++0x03 line.long 0x00 "FMPI2C_TIMEOUTR,Timeout register" bitfld.long 0x00 31. " TEXTEN ,Extended clock timeoout enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B" bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled" bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "SCL low,SCL/SDA high" textline " " hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A" endif if (((per.l(ad:0x40006000+0x08))&0x8000)==0x00)&&(((per.l(ad:0x40006000+0x0C))&0x8000)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "FMPI2C_ISR,Interrupt And Status Register" bitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" bitfld.long 0x00 12. " TIMEOUT ,Timeout or TLOW detection flag" "Not occurred,Occurred" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" textline " " bitfld.long 0x00 9. " ARLO ,ARbitration lost" "Not occurred,Occurred" bitfld.long 0x00 8. " BERR ,Bus error" "No error,Error" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed" bitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected" bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received" bitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty" textline " " bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty" else rgroup.long 0x18++0x03 line.long 0x00 "FMPI2C_ISR,Interrupt And Status Register" hexmask.long.byte 0x00 17.--23. 1. " ADDCODE ,Address match code" bitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read" bitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy" bitfld.long 0x00 13. " ALERT ,SMBus alert" "No alert,Alert" textline " " bitfld.long 0x00 12. " TIMEOUT ,Timeout or TLOW detection flag" "Not occurred,Occurred" bitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error" bitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred" bitfld.long 0x00 9. " ARLO ,ARbitration lost" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " BERR ,Bus error" "No error,Error" bitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed" bitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected" bitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received" textline " " bitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched" bitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes" bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty" bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty" endif wgroup.long 0x1C++0x03 line.long 0x00 "FMPI2C_ICR,Interrupt clear register" bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear" bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear" bitfld.long 0x00 11. " PECCF ,PEC error flag clear" "No effect,Clear" bitfld.long 0x00 10. " OVRCF ,Overrun/underrun flag clear" "No effect,Clear" textline " " bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear" bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear" bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear" bitfld.long 0x00 4. " NAKCF ,Not acknowledge flag clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear" if (((per.l(ad:0x40006000))&0x800000)==0x800000) rgroup.long 0x20++0x03 line.long 0x00 "FMPI2C_PECR,PEC Register" hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register" else rgroup.long 0x20++0x03 line.long 0x00 "FMPI2C_PECR,PEC Register" endif hgroup.long 0x24++0x03 hide.long 0x00 "FMPI2C_RXDR,Receive Data Register" in if ((per.l(ad:0x40006000+0x18)&0x01)==0x00) rgroup.long 0x28++0x03 line.long 0x00 "FMPI2C_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" else group.long 0x28++0x03 line.long 0x00 "FMPI2C_TXDR,Transmit Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data" endif width 0x0B tree.end tree.end endif tree.open "I2C (Inter-Integrated Circuit)" tree "I2C 1" base ad:0x40005400 width 11. if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1) group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start" bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "I2C_CR2,Control Register 2" bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last" bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled" textline " " sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC") bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..." textline " " elif (cpuis("STM32F2*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..." textline " " elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F411*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..." textline " " elif (cpuis("STM32F4*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..." textline " " else bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..." endif if (((per.w((ad:0x40005400+0x08)))&0x8000)==0x8000) group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address" else group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address" endif if (((per.w((ad:0x40005400+0x0C)))&0x1)==0x1) group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" else group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" endif hgroup.word 0x10++0x01 hide.word 0x00 "I2C_DR,Data Register" in hgroup.word 0x14++0x01 hide.word 0x00 "I2C_SR1,Status Register 1" in if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1) rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" else rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2" textline " " bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header" bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address" textline " " bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" endif if (((per.l(ad:0x40005400))&0x1)==0x1) if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1) rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif rgroup.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) rgroup.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif else if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1) group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif group.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) group.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif endif width 0x0B tree.end tree "I2C 2" base ad:0x40005800 width 11. if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1) group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start" bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "I2C_CR2,Control Register 2" bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last" bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled" textline " " sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC") bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..." textline " " elif (cpuis("STM32F2*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..." textline " " elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F411*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..." textline " " elif (cpuis("STM32F4*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..." textline " " else bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..." endif if (((per.w((ad:0x40005800+0x08)))&0x8000)==0x8000) group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address" else group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address" endif if (((per.w((ad:0x40005800+0x0C)))&0x1)==0x1) group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" else group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" endif hgroup.word 0x10++0x01 hide.word 0x00 "I2C_DR,Data Register" in hgroup.word 0x14++0x01 hide.word 0x00 "I2C_SR1,Status Register 1" in if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1) rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" else rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2" textline " " bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header" bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address" textline " " bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" endif if (((per.l(ad:0x40005800))&0x1)==0x1) if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1) rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif rgroup.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) rgroup.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif else if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1) group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif group.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) group.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif endif width 0x0B tree.end sif !cpuis("STM32F410*") tree "I2C 3" base ad:0x40005C00 width 11. if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1) group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" else group.word 0x00++0x01 line.word 0x00 "I2C_CR1,Control Register 1" bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset" bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low" textline " " bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer" bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte" textline " " bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled" bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released" textline " " bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start" bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes" textline " " bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled" bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled" bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host" textline " " bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus" bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled" endif group.word 0x04++0x01 line.word 0x00 "I2C_CR2,Control Register 2" bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last" bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled" textline " " sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC") bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..." textline " " elif (cpuis("STM32F2*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..." textline " " elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F411*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..." textline " " elif (cpuis("STM32F4*")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..." textline " " elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")) bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..." textline " " else bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..." endif if (((per.w((ad:0x40005C00+0x08)))&0x8000)==0x8000) group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address" else group.word 0x08++0x01 line.word 0x00 "I2C_OAR1,Own Address Register 1" bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit" hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address" endif if (((per.w((ad:0x40005C00+0x0C)))&0x1)==0x1) group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" else group.word 0x0C++0x01 line.word 0x00 "I2C_OAR2,Own Address Register 2" bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2" endif hgroup.word 0x10++0x01 hide.word 0x00 "I2C_DR,Data Register" in hgroup.word 0x14++0x01 hide.word 0x00 "I2C_SR1,Status Register 1" in if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1) rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" else rgroup.word 0x18++0x01 line.word 0x00 "I2C_SR2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register" bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2" textline " " bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header" bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address" textline " " bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call" bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted" textline " " bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy" bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master" endif if (((per.l(ad:0x40005C00))&0x1)==0x1) if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1) rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else rgroup.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif rgroup.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) rgroup.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif else if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1) group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" textline " " hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode" else group.word 0x1C++0x01 line.word 0x00 "I2C_CCR,Clock Control Register" bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast" bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9" endif group.word 0x20++0x01 line.word 0x00 "I2C_TRISE,TRISE Register" bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")) group.word 0x24++0x01 line.word 0x00 "I2C_FLTR,I2C FLTR register" bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled" bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1" endif endif width 0x0B tree.end endif tree.end tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") tree "USART 1" base ad:0x40011000 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011000+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011000+0x14)&0x20)==0x20)||((per.l(ad:0x40011000+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40011000+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end tree "USART 2" base ad:0x40004400 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004400+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004400+0x14)&0x20)==0x20)||((per.l(ad:0x40004400+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40004400+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") tree "USART 3" base ad:0x40004800 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004800+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004800+0x14)&0x20)==0x20)||((per.l(ad:0x40004800+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40004800+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end endif sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") tree "UART 4" base ad:0x40004C00 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004C00+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004C00+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end tree "UART 5" base ad:0x40005000 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40005000+0x10)&0x4000)==0x4000)||((per.l(ad:0x40005000+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end endif sif !cpuis("STM32F410T*")&&!cpuis("STM32F412C*")&&!cpuis("STM32F413C*")&&!cpuis("STM32F423CH") tree "USART 6" base ad:0x40011400 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011400+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011400+0x14)&0x20)==0x20)||((per.l(ad:0x40011400+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40011400+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end endif sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") tree "UART 7" base ad:0x40007800 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40007800+0x10)&0x4000)==0x4000)||((per.l(ad:0x40007800+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end sif cpuis("STM32F413V*")||cpuis("STM32F413Z*")||cpuis("STM32F423VH")||cpuis("STM32F423ZH")||(cpuis("STM32F469*")&&!cpuis("STM32F469V*")&&!cpuis("STM32F469Z*"))||(cpuis("STM32F479*")&&!cpuis("STM32F479V*")&&!cpuis("STM32F479Z*")) tree "UART 8" base ad:0x40007C00 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40007C00+0x10)&0x4000)==0x4000)||((per.l(ad:0x40007C00+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end endif sif cpuis("STM32F413V*")||cpuis("STM32F413Z*")||cpuis("STM32F423VH")||cpuis("STM32F423ZH") tree "UART 9" base ad:0x40011800 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011800+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011800+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end tree "UART 10" base ad:0x40011C00 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011C00+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011C00+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end endif endif else tree "USART 1" base ad:0x40011000 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011000+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011000+0x14)&0x20)==0x20)||((per.l(ad:0x40011000+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40011000+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end tree "USART 2" base ad:0x40004400 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004400+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004400+0x14)&0x20)==0x20)||((per.l(ad:0x40004400+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40004400+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end tree "USART 3" base ad:0x40004800 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004800+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004800+0x14)&0x20)==0x20)||((per.l(ad:0x40004800+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40004800+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end tree "UART 4" base ad:0x40004C00 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40004C00+0x10)&0x4000)==0x4000)||((per.l(ad:0x40004C00+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end tree "UART 5" base ad:0x40005000 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40005000+0x10)&0x4000)==0x4000)||((per.l(ad:0x40005000+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end tree "USART 6" base ad:0x40011400 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40011400+0x10)&0x4000)==0x4000)||((per.l(ad:0x40011400+0x14)&0x20)==0x20)||((per.l(ad:0x40011400+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" textline " " bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5" bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High" bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data" textline " " bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output" textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled" bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" if (((per.l((ad:0x40011400+0x14)))&0x20)==0x20) group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value" else group.long 0x18++0x3 line.long 0x00 "USART_GTPR,Guard time and prescaler register" hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value" endif width 0x0B tree.end tree "UART 7" base ad:0x40007800 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40007800+0x10)&0x4000)==0x4000)||((per.l(ad:0x40007800+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end tree "UART 8" base ad:0x40007C00 width 12. group.long 0x00++0x03 line.long 0x00 "USART_SR,Status register" sif cpuis("STM32F4*") else bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change" textline " " endif bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected" textline " " sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")) rbitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" else bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred" endif textline " " bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Completed" textline " " bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "No,Yes" textline " " sif cpuis("STM32F4*") rbitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" rbitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" rbitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected" textline " " rbitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" rbitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" else bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle" bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun" bitfld.long 0x00 2. " NE ,Noise Error Flag" "No error,Error" textline " " bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error" bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error" endif hgroup.long 0x04++0x03 hide.long 0x00 "USART_DR,Data register" in group.long 0x08++0x03 line.long 0x00 "USART_BRR,Baud rate register" hexmask.long.word 0x00 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV" bitfld.long 0x00 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STM32F4*")) if (((per.l(ad:0x40007C00+0x10)&0x4000)==0x4000)||((per.l(ad:0x40007C00+0x14)&0x02)==0x02)) group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,?..." textline " " endif bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;nStop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif else group.long 0x0C++0x03 line.long 0x00 "USART_CR1,Control register 1" bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8" bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled" bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop" bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark" textline " " bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled" bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd" bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled" textline " " bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute" bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break" textline " " endif group.long 0x10++0x07 line.long 0x00 "USART_CR2,Control register 2" bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,,2,?..." textline " " bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled" bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit" textline " " bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh" line.long 0x04 "USART_CR3,Control register 3" bitfld.long 0x04 11. " ONEBIT ,One sample bit method enable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " else bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled" bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled" textline " " endif bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected" bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power" textline " " bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled" width 0x0B tree.end endif tree.end sif (cpuis("STM32F410*")) tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1/I2S1" base ad:0x40013000 width 13. if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40013000+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40013000+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40013000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end sif cpuis("STM32F410C*")||cpuis("STM32F410R*") tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 5/I2S5" base ad:0x40015400 width 13. if (((per.w((ad:0x40015400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40015400+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40015400+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40015400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40015400+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40015400+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40015400+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40015400+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40015400+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40015400+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40015400+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40015400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end endif tree.end elif (cpuis("STM32F411?C")||cpuis("STM32F411?E")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1/I2S1" base ad:0x40013000 width 13. if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40013000+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40013000+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40013000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 3/I2S3" base ad:0x40003C00 width 13. if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003C00+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 4/I2S4" base ad:0x40013400 width 13. if (((per.w((ad:0x40013400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013400+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40013400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013400+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40013400+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40013400+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40013400+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40013400+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40013400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 5/I2S5" base ad:0x40015000 width 13. if (((per.w((ad:0x40015000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40015000+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40015000+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40015000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40015000+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40015000+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40015000+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40015000+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40015000+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40015000+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40015000+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40015000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "I2S2ext" base ad:0x40003400 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40003400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree "I2S3ext" base ad:0x40004000 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40004000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree.end elif (cpuis("STM32F469*")||cpuis("STM32F479*")) tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1" base ad:0x40013000 width 12. if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 3/I2S3" base ad:0x40003C00 width 13. if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003C00+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 4" base ad:0x40013400 width 12. if ((per.w((ad:0x40013400+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40013400+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end sif !cpuis("STM32F469V*")&&!cpuis("STM32F469Z*")&&!cpuis("STM32F479V*")&&!cpuis("STM32F479Z*") tree "SPI 5" base ad:0x40015000 width 12. if ((per.w((ad:0x40015000+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40015000+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 6" base ad:0x40015400 width 12. if ((per.w((ad:0x40015400+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40015400+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end endif tree "I2S2ext" base ad:0x40003400 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40003400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree "I2S3ext" base ad:0x40004000 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40004000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree.end elif (cpuis("STM32F411*")||cpuis("STM32F401V*")||cpuis("STM32F427V*")||cpuis("STM32F429V*")||cpuis("STM32F437V*")||cpuis("STM32F439V*")) tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1/I2S1" base ad:0x40013000 width 13. if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40013000+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013000+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40013000+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40013000+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40013000+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40013000+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40013000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 3/I2S3" base ad:0x40003C00 width 13. if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003C00+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 4/I2S4" base ad:0x40013400 width 13. if (((per.w((ad:0x40013400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013400+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40013400+0x1C))&0x800)==0x0)&&((per.w((ad:0x40013400+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40013400+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40013400+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40013400+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40013400+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40013400+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40013400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "I2S2ext" base ad:0x40003400 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40003400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree "I2S3ext" base ad:0x40004000 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40004000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree.end elif cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*") tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1/I2S1" base ad:0x40013000 width 12. if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 3/I2S3" base ad:0x40003C00 width 13. if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003C00+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 4/I2S4" base ad:0x40013400 width 12. if ((per.w((ad:0x40013400+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40013400+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 5/I2S5" base ad:0x40015000 width 12. if ((per.w((ad:0x40015000+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40015000+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 6/I2S6" base ad:0x40015400 width 12. if ((per.w((ad:0x40015400+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40015400+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40015400+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "I2S2ext" base ad:0x40003400 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40003400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree "I2S3ext" base ad:0x40004000 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40004000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree.end else tree.open "SPI (Serial Peripheral Interface)" tree "SPI 1/I2S1" base ad:0x40013000 width 12. if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" endif if ((per.w((ad:0x40013000+0x04))&0x10)==0x00) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" sif (cpuis("STM32F7*")) bitfld.word 0x00 3. " NSSP ,NSS pulse management" "Not generated,Generated" endif textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" endif group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif width 0x0B tree.end tree "SPI 2/I2S2" base ad:0x40003800 width 13. if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003800+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003800+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003800+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003800+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003800+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "SPI 3/I2S3" base ad:0x40003C00 width 13. if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " textline " " bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional" bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled" textline " " bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled" bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register" textline " " bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit" bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only" textline " " bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled" bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin" textline " " bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB" bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256" bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master" textline " " bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else sif (cpuis("STM32F7*")) group.word 0x00++0x01 line.word 0x00 "SPI_CR1,SPI control register 1" bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1" bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data" else hgroup.word 0x00++0x01 hide.word 0x00 "SPI_CR1,SPI control register 1" endif endif if (((per.w((ad:0x40003C00+0x1C))&0x800)==0x0)&&((per.w((ad:0x40003C00+0x4))&0x10)==0x10)) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" elif ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" sif (cpuis("STM32F7*")) bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd" bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd" textline " " bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit" bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" textline " " endif bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI" textline " " bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled" bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" else group.word 0x04++0x01 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" textline " " bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.word 0x08++0x01 hide.word 0x00 "SPI_SR,SPI status register" in else if ((per.w((ad:0x40003C00+0x1C))&0x800)==0x0) rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" textline " " bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault" textline " " bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,No match" textline " " bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" else rgroup.word 0x08++0x01 line.word 0x00 "SPI_SR,SPI status register" bitfld.word 0x00 8. " TIFRFE ,TI frame format error" "No error,Error" bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy" textline " " bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun" textline " " bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred" textline " " bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right" bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "No,Yes" endif endif if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x0)&&(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register" else group.word 0x0C++0x01 line.word 0x00 "SPI_DR,SPI data register" endif if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0)) group.word 0x10++0x01 line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hexmask.word.byte 0x00 0.--7. 1. " RXCRC ,Rx CRC register" endif if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800) rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" else rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" hexmask.word.byte 0x00 0.--7. 1. " TXCRC ,Tx CRC register" endif else rgroup.word 0x14++0x01 line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" rgroup.word 0x18++0x01 line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif else hgroup.word 0x10++0x01 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x01 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x01 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" endif if ((((per.w((ad:0x40003C00+0x1C)))&0x800)==0x00)) group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")||cpuis("STM32F412*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" textline " " textline " " textline " " else group.word 0x1C++0x01 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" sif (cpuis("STM32F7*")||cpuis("STM32F410*")) bitfld.word 0x00 12. " ASTRTEN ,Asynchronous start enable" "Disabled,Enabled" textline " " endif bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Transmit,Master/Receive" bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" endif if (((per.w((ad:0x40003C00+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0xB tree.end tree "I2S2ext" base ad:0x40003400 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40003400+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree "I2S3ext" base ad:0x40004000 width 13. hgroup.word 0x00++0x1 hide.word 0x00 "SPI_CR1,SPI control register 1" group.word 0x04++0x1 line.word 0x00 "SPI_CR2,SPI control register 2" bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked" bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled" textline " " bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled" hgroup.word 0x08++0x1 hide.word 0x00 "SPI_SR,SPI status register" in group.word 0x0C++0x1 line.word 0x00 "SPI_DR,SPI data register" hgroup.word 0x10++0x1 hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register" hgroup.word 0x14++0x1 hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register" hgroup.word 0x18++0x1 hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register" group.word 0x1C++0x1 line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register" bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,?..." bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization (PCM standard only)" "Short,Long" textline " " bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM" bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High" textline " " bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed" bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit" if (((per.w((ad:0x40004000+0x1C)))&0xB00)==(0xA00||0xB00)) group.word 0x20++0x01 line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled" bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1" hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler" else hgroup.word 0x20++0x01 hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register" endif width 0x0B tree.end tree.end endif sif (cpuis("STM32F446*")) tree "SPDIFRX (SPDIF Receiver Interface)" base ad:0x40004000 width 14. group.long 0x00++0x07 line.long 0x00 "SPDIFRX_CR,Control Register" bitfld.long 0x00 16.--18. " INSEL ,SPDIFRX input selection" "SPDIFRX_IN1,SPDIFRX_IN2,SPDIFRX_IN3,SPDIFRX_IN4,?..." bitfld.long 0x00 14. " WFA ,Wait For Activity" "No,Yes" bitfld.long 0x00 12.--13. " NBTR ,Maximum allowed re-tries during synchronization phase" "No re-try,3 re-tries,15 re-tries,63 re-tries" bitfld.long 0x00 11. " CHSEL ,Channel Selection" "Channel A,Channel B" textline " " bitfld.long 0x00 10. " CBDMAEN ,Control Buffer DMA Enable for control flow" "Disabled,Enabled" bitfld.long 0x00 9. " PTMSK ,Mask of Preamble Type bits" "Not masked,Masked" bitfld.long 0x00 8. " CUMSK ,Mask of channel status and user bits" "Not masked,Masked" bitfld.long 0x00 7. " VMSK ,Mask of Validity bit" "Not masked,Masked" textline " " bitfld.long 0x00 6. " PMSK ,Mask Parity error bit" "Not masked,Masked" bitfld.long 0x00 4.--5. " DRFMT ,RX Data format" "LSB,MSB,2 * 16-bit -> 32-bit,?..." bitfld.long 0x00 3. " RXSTEO ,Stereo Mode" "MONO,STEREO" bitfld.long 0x00 2. " RXDMAEN ,Receiver DMA Enable for data flow" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " SPDIFRXEN ,Peripheral Block Enable" "Disabled,Enabled SPDIFRX Synchronization,,Enabled SPDIF Receiver" textline " " line.long 0x04 "SPDIFRX_IMR,Interrupt Mask Register" bitfld.long 0x04 6. " IFEIE ,Serial Interface Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " SYNCDIE ,Synchronization Done Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " SBLKIE ,Synchronization Block Detected Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " OVRIE ,Overrun error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PERRIE ,Parity error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " CSRNEIE ,Control Buffer Ready Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " RXNEIE ,RXNE Interrupt Enable" "Disabled,Enabled" rgroup.long 0x08++0x03 line.long 0x00 "SPDIFRX_SR,Status Register" hexmask.long.word 0x00 16.--30. 1. " WIDTH5 ,Duration of 5 symbols counted with SPDIFRX_CLK" bitfld.long 0x00 8. " TERR ,Time-out error" "No error,Error" bitfld.long 0x00 7. " SERR ,Synchronization error" "No error,Error" bitfld.long 0x00 6. " FERR ,Framing error" "No error,Error" textline " " bitfld.long 0x00 5. " SYNCD ,Synchronization Done" "Not completed,Completed" bitfld.long 0x00 4. " SBD ,Synchronization Block Detected" "Not detected,Detected" bitfld.long 0x00 3. " OVR ,Overrun error" "No overrun,Overrun" bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error" textline " " bitfld.long 0x00 1. " CSRNE ,The Control Buffer register is not empty" "Empty,Not empty" bitfld.long 0x00 0. " RXNE ,Read data register not empty" "Empty,Not empty" wgroup.long 0x0C++0x03 line.long 0x00 "SPDIFRX_IFCR,Interrupt Flag Clear Register" bitfld.long 0x00 5. " SYNCDCF ,Clears the Synchronization Done flag" "No effect,Clear" bitfld.long 0x00 4. " SBDCF ,Clears the Synchronization Block Detected flag" "No effect,Clear" bitfld.long 0x00 3. " OVRCF ,Clears the Overrun error flag" "No effect,Clear" bitfld.long 0x00 2. " PERRCF ,Clears the Parity error flag" "No effect,Clear" if ((per.l(ad:0x40004000)&0x30)==0x00) rgroup.long 0x10++0x03 line.long 0x00 "SPDIFRX_DR,Data Input Register" bitfld.long 0x00 28.--29. " PT ,Preamble Type received" "Not used,Preamble B,Preamble M,Preamble W" bitfld.long 0x00 27. " C ,Channel Status bit" "0,1" bitfld.long 0x00 26. " U ,User bit" "0,1" bitfld.long 0x00 25. " V ,Validity bit" "0,1" textline " " bitfld.long 0x00 24. " PE ,Parity Error bit" "0,1" hexmask.long.tbyte 0x00 0.--23. 1. " DR ,Data value" elif ((per.l(ad:0x40004000)&0x30)==0x10) rgroup.long 0x10++0x03 line.long 0x00 "SPDIFRX_DR,Data Input Register" hexmask.long.tbyte 0x00 8.--31. 1. " DR ,Data value" bitfld.long 0x00 4.--5. " PT ,Preamble Type received" "Not used,Preamble B,Preamble M,Preamble W" bitfld.long 0x00 3. " C ,Channel Status bit" "0,1" bitfld.long 0x00 2. " U ,User bit" "0,1" textline " " bitfld.long 0x00 1. " V ,Validity bit" "0,1" bitfld.long 0x00 0. " PE ,Parity Error bit" "0,1" elif ((per.l(ad:0x40004000)&0x30)==0x20) rgroup.long 0x10++0x03 line.long 0x00 "SPDIFRX_DR,Data Input Register" hexmask.long.word 0x00 16.--31. 1. " DRNL2 ,Data value (Channel A)" hexmask.long.word 0x00 0.--15. 1. " DRNL1 ,Data value (Channel B)" endif rgroup.long 0x14++0x07 line.long 0x00 "SPDIFRX_CSR,Channel Status Register" bitfld.long 0x00 24. " SOB ,Start Of Block (CS[0] correspond)" "Not first,First" hexmask.long.byte 0x00 16.--23. 1. " CS ,Channel A status information" hexmask.long.word 0x00 0.--15. 1. " USR ,User data information" line.long 0x04 "SPDIFRX_DIR,Debug Information Register" hexmask.long.word 0x04 16.--28. 1. " TLO ,Threshold LOW (TLO = 1.5 * UI / TSPDIFRX_CLK)" hexmask.long.word 0x04 0.--12. 1. " THI ,Threshold HIGH (THI = 2.5 * UI / TSPDIFRX_CLK)" width 0x0B tree.end endif sif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H")) tree.open "SAI (Serial Audio Interface)" tree "Block A" base ad:0x40015800 width 12. sif (cpuis("STM32F446*")||cpuis("STM32F7*")) group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" "No synchronization,Block A,Block B,?..." textline " " elif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." textline " " endif group.long 0x04++0x03 line.long 0x00 "SAI_ACR1,SAI A Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015800+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_AFRCR,SAI A Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_ASLOTR,SAI A Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_AIM,SAI A Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015800+0x04))&0x01)==0x00) if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015800+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015800+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_ADR,SAI A Data register" width 0x0B tree.end tree "Block B" base ad:0x40015820 width 12. group.long 0x04++0x03 line.long 0x00 "SAI_BCR1,SAI B Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015820+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_BFRCR,SAI B Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_BSLOTR,SAI B Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_BIM,SAI B Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015820+0x04))&0x01)==0x00) if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015820+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015820+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_BDR,SAI B Data register" width 0x0B tree.end tree.end elif (cpuis("STM32F446*")) tree.open "SAI (Serial Audio Interface)" tree "SAI_1" tree "Block A" base ad:0x40015800 width 12. sif (cpuis("STM32F446*")||cpuis("STM32F7*")) group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" "No synchronization,Block A,Block B,?..." textline " " elif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." textline " " endif group.long 0x04++0x03 line.long 0x00 "SAI_ACR1,SAI A Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015800+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_AFRCR,SAI A Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_ASLOTR,SAI A Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_AIM,SAI A Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015800+0x04))&0x01)==0x00) if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015800+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015800+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015800+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_ADR,SAI A Data register" width 0x0B tree.end tree "Block B" base ad:0x40015820 width 12. group.long 0x04++0x03 line.long 0x00 "SAI_BCR1,SAI B Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015820+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_BFRCR,SAI B Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_BSLOTR,SAI B Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_BIM,SAI B Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015820+0x04))&0x01)==0x00) if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015820+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015820+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015820+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_BDR,SAI B Data register" width 0x0B tree.end tree.end tree "SAI_2" tree "Block A" base ad:0x40015C00 width 12. sif (cpuis("STM32F446*")||cpuis("STM32F7*")) group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." bitfld.long 0x00 0.--1. " SYNCIN ,Synchronization inputs" "No synchronization,Block A,Block B,?..." textline " " elif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x00++0x03 line.long 0x00 "SAI_GCR,Global configuration register" bitfld.long 0x00 4.--5. " SYNCOUT ,Synchronization outputs" "No synchronization,Block A,Block B,?..." textline " " endif group.long 0x04++0x03 line.long 0x00 "SAI_ACR1,SAI A Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIAEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIAEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015C00+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_ACR2,SAI A Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_AFRCR,SAI A Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_ASLOTR,SAI A Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_AIM,SAI A Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015C00+0x04))&0x01)==0x00) if (((per.l(ad:0x40015C00+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015C00+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015C00+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_ASR,SAI A Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015C00+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015C00+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_ACLRFR,SAI A Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_ADR,SAI A Data register" width 0x0B tree.end tree "Block B" base ad:0x40015C20 width 12. group.long 0x04++0x03 line.long 0x00 "SAI_BCR1,SAI B Configuration register 1" bitfld.long 0x00 20.--23. " MCKDIV ,Master clock divider" "/1,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" bitfld.long 0x00 19. " NODIV ,No divider" "No,Yes" bitfld.long 0x00 17. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SAIBEN ,Audio block enable" "Disabled,Enabled" bitfld.long 0x00 13. " OUTDRIV ,Output drive" "On SAIBEN,Immediately" bitfld.long 0x00 12. " MONO ,Mono mode" "Stereo,Mono" textline " " sif (cpuis("STM32F7*")||cpuis("STM32F446*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous (int),Synchronous (ext),?..." elif (cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")) bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,?..." else bitfld.long 0x00 10.--11. " SYNCEN ,Synchronization enable" "Asynchronous,Synchronous,,Not used" endif textline " " bitfld.long 0x00 9. " CKSTR ,Clock strobing edge" "Falling,Rising" bitfld.long 0x00 8. " LSBFIRST ,Least significant bit first" "MSB,LSB" textline " " bitfld.long 0x00 5.--7. " DS ,Data size" ",,8-bit,10-bit,16-bit,20-bit,24-bit,32-bit" sif (cpuis("STM32F7*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,SPDIF,AC97,?..." else bitfld.long 0x00 2.--3. " PRTCFG ,Protocol configuration" "Free,,AC97,?..." endif textline " " bitfld.long 0x00 0.--1. " MODE ,Audio block mode" "Master transmitter,Master receiver,Slave transmitter,Slave receiver" if (((per.l(ad:0x40015C20+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" bitfld.long 0x00 7.--12. " MUTECNT ,Mute counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." else group.long 0x08++0x03 line.long 0x00 "SAI_BCR2,SAI B Configuration register 2" bitfld.long 0x00 14.--15. " COMP ,Companding mode" "No companding,,u-Law,A-Law" bitfld.long 0x00 13. " CPL ,Complement bit" "1s complement,2s complement" textline " " bitfld.long 0x00 6. " MUTEVAL ,Mute value" "Bit value 0,Last values" bitfld.long 0x00 5. " MUTE ,Mute" "Disabled,Enabled" bitfld.long 0x00 4. " TRIS ,Tristate management on data line" "Driven,Released" textline " " bitfld.long 0x00 3. " FFLUSH ,FIFO flush" "Not flushed,Flushed" bitfld.long 0x00 0.--2. " FTH ,FIFO threshold" "Empty,1/4 FIFO,1/2 FIFO,3/4 FIFO,Full,?..." endif group.long 0x0C++0x0B line.long 0x00 "SAI_BFRCR,SAI B Frame configuration register" bitfld.long 0x00 18. " FSOFF ,Frame synchronization offset" "First bit,One bit before" bitfld.long 0x00 17. " FSPOL ,Frame synchronization polarity" "Low/Falling,High/Rising" rbitfld.long 0x00 16. " FSDEF ,Frame synchronization definition" "Start frame,Start frame+channel" textline " " hexmask.long.byte 0x00 8.--14. 1. " FSALL ,Frame synchronization active level length" hexmask.long.byte 0x00 0.--7. 1. " FRL ,Frame length" line.long 0x04 "SAI_BSLOTR,SAI B Slot register" bitfld.long 0x04 31. " SLOTEN[15] ,Slot 15 enable" "Disabled,Enabled" bitfld.long 0x04 30. " SLOTEN[14] ,Slot 14 enable" "Disabled,Enabled" bitfld.long 0x04 29. " SLOTEN[13] ,Slot 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " SLOTEN[12] ,Slot 12 enable" "Disabled,Enabled" bitfld.long 0x04 27. " SLOTEN[11] ,Slot 11 enable" "Disabled,Enabled" bitfld.long 0x04 26. " SLOTEN[10] ,Slot 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " SLOTEN[9] ,Slot 9 enable" "Disabled,Enabled" bitfld.long 0x04 24. " SLOTEN[8] ,Slot 8 enable" "Disabled,Enabled" bitfld.long 0x04 23. " SLOTEN[7] ,Slot 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " SLOTEN[6] ,Slot 6 enable" "Disabled,Enabled" bitfld.long 0x04 21. " SLOTEN[5] ,Slot 5 enable" "Disabled,Enabled" bitfld.long 0x04 20. " SLOTEN[4] ,Slot 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " SLOTEN[3] ,Slot 3 enable" "Disabled,Enabled" bitfld.long 0x04 18. " SLOTEN[2] ,Slot 2 enable" "Disabled,Enabled" bitfld.long 0x04 17. " SLOTEN[1] ,Slot 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " SLOTEN[0] ,Slot 0 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8.--11. " NBSLOT ,Number of slots in an audio frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--7. " SLOTSZ ,Slot size" "Data size,16-bit,32-bit,?..." bitfld.long 0x04 0.--4. " FBOFF ,First bit offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "SAI_BIM,SAI B Interrupt mask register 2" bitfld.long 0x08 6. " LFSDETIE ,Late frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " AFSDETIE ,Anticipated frame synchronization detection interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " CNRDYIE ,Codec not ready interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FREQIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " WCKCFGIE ,Wrong clock configuration interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " MUTEDETIE ,Mute detection interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " OVRUDRIE ,Overrun/underrun interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40015C20+0x04))&0x01)==0x00) if (((per.l(ad:0x40015C20+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif else if (((per.l(ad:0x40015C20+0x04))&0xC)==0x00) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." bitfld.long 0x00 6. " LFSDET ,Late frame synchronization detection" "No error,Error" bitfld.long 0x00 5. " AFSDET ,Anticipated frame synchronization detection" "No error,Error" textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" elif (((per.l(ad:0x40015C20+0x04))&0xC)==0x8) rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 4. " CNRDY ,Codec not ready" "Ready,Not ready" bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" else rgroup.long 0x18++0x03 line.long 0x00 "SAI_BSR,SAI B Status register" bitfld.long 0x00 16.--18. " FLTH ,FIFO level threshold" "Empty,FIFO <= 1/4,1/4 < FIFO <= 1/2,1/2 < FIFO <= 3/4,3/4 < FIFO,Full,?..." textline " " bitfld.long 0x00 3. " FREQ ,FIFO request" "Not requested,Requested" bitfld.long 0x00 2. " WCKCFG ,Wrong clock configuration" "Correct,Not correct" textline " " bitfld.long 0x00 1. " MUTEDET ,Mute detection" "Not detected,Detected" bitfld.long 0x00 0. " OVRUDR ,Overrun/underrun error" "No error,Error" endif endif if (((per.l(ad:0x40015C20+0x04))&0xC)==0x00) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 6. " CLFSDET ,Clear late frame synchronization detection flag" "No effect,Clear" bitfld.long 0x00 5. " CAFSDET ,Clear anticipated frame synchronization detection flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" elif (((per.l(ad:0x40015C20+0x04))&0xC)==0x8) wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" bitfld.long 0x00 4. " CCNRDY ,Clear codec not ready flag" "No effect,Clear" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" else wgroup.long 0x1C++0x03 line.long 0x00 "SAI_BCLRFR,SAI B Clear flag register" textline " " bitfld.long 0x00 2. " CWCKCFG ,Clear wrong clock configuration flag" "No effect,Clear" bitfld.long 0x00 1. " CMUTEDET ,Clear mute detection flag" "No effect,Clear" bitfld.long 0x00 0. " COVRUDR ,Clear overrun/underrun" "No effect,Clear" endif group.long 0x20++0x03 line.long 0x00 "SAI_BDR,SAI B Data register" width 0x0B tree.end tree.end tree.end endif sif (!cpuis("STM32F401C*")&&!cpuis("STM32F410*")) tree "SDIO (SDIO Interface)" base ad:0x40012C00 width 14. group.long 0x00++0xF line.long 0x00 "SDIO_POWER,SDIO Power Control Register" sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Power-off,,Power-up,Power-on" textline " " else bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Off,,,On" textline " " endif line.long 0x04 "SDIO_CLKCR,SDI Clock Control Register" bitfld.long 0x04 14. " HWFC_EN ,HW Flow Control enable" "Disabled,Enabled" bitfld.long 0x04 13. " NEGEDGE ,SDIO_CK dephasing selection bit" "Rising edge,Falling edge" textline " " bitfld.long 0x04 11.--12. " WIDBUS ,Wide bus mode enable bit" "SDIO_D0,SDIO_D[3:0],SDIO_D[7:0],?..." bitfld.long 0x04 10. " BYPASS ,Clock divider bypass enable bit" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled/bus active" bitfld.long 0x04 8. " CLKEN ,Clock enable bit" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 0.--7. 1. " CLKDIV ,Clock divide factor" line.long 0x08 "SDIO_ARG,SDIO Argument Register" line.long 0x0C "SDIO_CMD,SDIO Command Register" sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x0C 14. " ATACMD ,CE-ATA command" "No transfer,CPSM transfers CMD61" bitfld.long 0x0C 13. " NIEN ,not Interrupt Enable" "Enabled,Disabled" textline " " bitfld.long 0x0C 12. " ENCMDCOMP1 ,Enable CMD completion" "Disabled,Enabled" textline " " endif bitfld.long 0x0C 11. " SDIOSUSPEND ,SD I/O suspend command" "Not suspended,Suspended" textline " " bitfld.long 0x0C 10. " CPSMEN ,Command path state machine (CPSM) Enable bit" "Disabled,Enabled" bitfld.long 0x0C 9. " WAITPEND ,CPSM Waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait" textline " " bitfld.long 0x0C 8. " WAITINT ,CPSM Waits for Interrupt Request" "Not requested,Requested" bitfld.long 0x0C 6.--7. " WAITRESP ,Wait for response bits" "No response,Short response,No response,Long response" textline " " bitfld.long 0x0C 0.--5. " CMDINDEX ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10++0x3 line.long 0x00 "SDIO_RESPCMD,SDIO Command Response Register" bitfld.long 0x00 0.--5. " RESPCMD ,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.l((ad:0x40012C00+0x0C))&0xC0)==0x40) rgroup.long 0x14++0x3 line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register" hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status[31:0]" hgroup.long 0x18++0x0B hide.long 0x00 "SDIO_RESP2,SDIO Response 2 Register" hide.long 0x04 "SDIO_RESP3,SDIO Response 3 Register" hide.long 0x08 "SDIO_RESP4,SDIO Response 4 Register" elif ((per.l((ad:0x40012C00+0x0C))&0xC0)==0xC0) rgroup.long 0x14++0xF line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register" hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status [127:96]" line.long 0x04 "SDIO_RESP2,SDIO Response 2 Register" hexmask.long 0x04 0.--31. 1. " CARDSTATUS2 ,Card Status [95:64]" line.long 0x08 "SDIO_RESP3,SDIO Response 3 Register" hexmask.long 0x08 0.--31. 1. " CARDSTATUS3 ,Card Status [63:32]" line.long 0x0C "SDIO_RESP4,SDIO Response 4 Register" hexmask.long 0x0C 0.--31. 1. " CARDSTATUS3 ,Card Status [31:0]" else hgroup.long 0x14++0xF hide.long 0x00 "SDIO_RESP1,SDIO Response 1 Register" hide.long 0x04 "SDIO_RESP2,SDIO Response 2 Register" hide.long 0x08 "SDIO_RESP3,SDIO Response 3 Register" hide.long 0x0C "SDIO_RESP4,SDIO Response 4 Register" endif group.long 0x24++0x0B line.long 0x00 "SDIO_DTIMER,SDIO Data Timer Register" line.long 0x04 "SDIO_DLEN,SDIO Data Length Register" hexmask.long 0x04 0.--24. 1. " DATALENGTH ,Data length value" line.long 0x08 "SDIO_DCTRL,SDIO Data Control Register" bitfld.long 0x08 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled" bitfld.long 0x08 10. " RWMOD ,Read wait mode" "Stopping SDIO_D2,Using SDIO_CK" textline " " bitfld.long 0x08 9. " RWSTOP ,Read wait stop" "Not stopped,Stopped" bitfld.long 0x08 8. " RWSTART ,Read wait start" "Not started,Started" textline " " bitfld.long 0x08 4.--7. " DBLOCKSIZE ,Data block size" "1 byte,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes,?..." bitfld.long 0x08 3. " DMAEN ,DMA enable bit" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " DTMODE ,Data transfer mode selection" "Block,Stream" bitfld.long 0x08 1. " DTDIR ,Data transfer direction selection" "Controller to card,Card to controller" textline " " bitfld.long 0x08 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled" rgroup.long 0x30++0x07 line.long 0x00 "SDIO_DCOUNT,SDIO Data Counter Register" hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value" line.long 0x04 "SDIO_STA,SDIO Status Register" sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x04 23. " CEATAEND ,CE-ATA command completion signal received for CMD61" "Not completed,Completed" textline " " endif bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "No interrupt,Interrupt" textline " " bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "Not available,Available" bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "Not available,Available" textline " " bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty" bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty" textline " " bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full" bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full" textline " " bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO Half Full: there are at least 8 words in the FIFO" "Not half full,Half full" bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO Half Empty: at least 8 words can be written into the FIFO" "Not half empty,Half empty" textline " " bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Not in progress,In progress" bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Not in progress,In progress" textline " " bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Not in progress,In progress" bitfld.long 0x04 10. " DBCKEND ,Data block sent/received" "Not sent/received,Sent/Received" textline " " sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x04 9. " STBITERR ,Start bit not detected on all data signals in wide bus mode" "No error,Error" textline " " endif bitfld.long 0x04 8. " DATAEND ,Data end" "No end,End" textline " " bitfld.long 0x04 7. " CMDSENT ,Command sent" "Not sent,Sent" bitfld.long 0x04 6. " CMDREND ,Command response received" "Not received,Received" textline " " bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No overrun,Overrun" bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No underrun,Underrun" textline " " bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout" bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout" textline " " bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received" "Not sent/received,Sent/received" bitfld.long 0x04 0. " CCRCFAIL ,Command response received" "Not received,Received" group.long 0x38++0x07 line.long 0x00 "SDIO_ICR,SDIO Interrupt Clear Register" sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x00 23. " CEATAENDC ,CEATAEND Flag Clear Bit" "Not cleared,Cleared" textline " " endif bitfld.long 0x00 22. " SDIOITC ,SDIOIT Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 10. " DBCKENDC ,DBCKEND Flag Clear Bit" "Not cleared,Cleared" textline " " sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x00 9. " STBITERRC ,STBITERR Flag Clear Bit" "Not cleared,Cleared" textline " " endif bitfld.long 0x00 8. " DATAENDC ,DATAEND Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 7. " CMDSENTC ,CMDSENT Flag Clear Bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 6. " CMDRENDC ,CMDREND Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 5. " RXOVERRC ,RXOVERR Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR Flag Clear Bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT Flag Clear Bit" "Not cleared,Cleared" bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL Flag Clear Bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL Flag Clear Bit" "Not cleared,Cleared" line.long 0x04 "SDIO_MASK,SDIO Mask Register" sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")) bitfld.long 0x04 23. " CEATAENDIE ,CE-ATA command completion signal received Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 22. " SDIOITIE ,SDIO Mode Interrupt Received Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 21. " RXDAVLIE ,Data available in Rx FIFO Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 20. " TXDAVLIE ,Data available in Tx FIFO Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 19. " RXFIFOEIE ,Rx FIFO Empty Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 18. " TXFIFOEIE ,Tx FIFO Empty Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " RXFIFOFIE ,Rx FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 16. " TXFIFOFIE ,Tx FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 15. " RXFIFOHFIE ,Rx FIFO Half Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " TXFIFOHEIE ,Tx FIFO Half Empty Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 13. " RXACTIE ,Data Receive Acting Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 12. " TXACTIE ,Data Transmit Acting Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " CMDACTIE ,Command Acting Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 10. " DBCKENDIE ,Data Block End Interrupt Enable" "Disabled,Enabled" textline " " sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x04 9. " STBITERRIE ,Start Bit Error Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 8. " DATAENDIE ,Data End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " CMDSENTIE ,Command Sent Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 6. " CMDRENDIE ,Command Response Received Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " RXOVERRIE ,Rx FIFO OverRun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 4. " TXUNDERRIE ,Tx FIFO UnderRun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " DTIMEOUTIE ,Data TimeOut Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " CTIMEOUTIE ,Command TimeOut Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 1. " DCRCFAILIE ,Data CRC Fail Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " CCRCFAILIE ,Command CRC Fail Interrupt Enable" "Disabled,Enabled" rgroup.long 0x48++0x03 line.long 0x00 "SDIO_FIFOCNT,SDIO FIFO Counter Register" hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO" hgroup.long 0x80++0x03 hide.long 0x00 "SDIO_FIFO0,SDIO Data FIFO Register 0" in hgroup.long 0x84++0x03 hide.long 0x00 "SDIO_FIFO1,SDIO Data FIFO Register 1" in hgroup.long 0x88++0x03 hide.long 0x00 "SDIO_FIFO2,SDIO Data FIFO Register 2" in hgroup.long 0x8C++0x03 hide.long 0x00 "SDIO_FIFO3,SDIO Data FIFO Register 3" in hgroup.long 0x90++0x03 hide.long 0x00 "SDIO_FIFO4,SDIO Data FIFO Register 4" in hgroup.long 0x94++0x03 hide.long 0x00 "SDIO_FIFO5,SDIO Data FIFO Register 5" in hgroup.long 0x98++0x03 hide.long 0x00 "SDIO_FIFO6,SDIO Data FIFO Register 6" in hgroup.long 0x9C++0x03 hide.long 0x00 "SDIO_FIFO7,SDIO Data FIFO Register 7" in hgroup.long 0xA0++0x03 hide.long 0x00 "SDIO_FIFO8,SDIO Data FIFO Register 8" in hgroup.long 0xA4++0x03 hide.long 0x00 "SDIO_FIFO9,SDIO Data FIFO Register 9" in hgroup.long 0xA8++0x03 hide.long 0x00 "SDIO_FIFO10,SDIO Data FIFO Register 10" in hgroup.long 0xAC++0x03 hide.long 0x00 "SDIO_FIFO11,SDIO Data FIFO Register 11" in hgroup.long 0xB0++0x03 hide.long 0x00 "SDIO_FIFO12,SDIO Data FIFO Register 12" in hgroup.long 0xB4++0x03 hide.long 0x00 "SDIO_FIFO13,SDIO Data FIFO Register 13" in hgroup.long 0xB8++0x03 hide.long 0x00 "SDIO_FIFO14,SDIO Data FIFO Register 14" in hgroup.long 0xBC++0x03 hide.long 0x00 "SDIO_FIFO15,SDIO Data FIFO Register 15" in hgroup.long 0xC0++0x03 hide.long 0x00 "SDIO_FIFO16,SDIO Data FIFO Register 16" in hgroup.long 0xC4++0x03 hide.long 0x00 "SDIO_FIFO17,SDIO Data FIFO Register 17" in hgroup.long 0xC8++0x03 hide.long 0x00 "SDIO_FIFO18,SDIO Data FIFO Register 18" in hgroup.long 0xCC++0x03 hide.long 0x00 "SDIO_FIFO19,SDIO Data FIFO Register 19" in hgroup.long 0xD0++0x03 hide.long 0x00 "SDIO_FIFO20,SDIO Data FIFO Register 20" in hgroup.long 0xD4++0x03 hide.long 0x00 "SDIO_FIFO21,SDIO Data FIFO Register 21" in hgroup.long 0xD8++0x03 hide.long 0x00 "SDIO_FIFO22,SDIO Data FIFO Register 22" in hgroup.long 0xDC++0x03 hide.long 0x00 "SDIO_FIFO23,SDIO Data FIFO Register 23" in hgroup.long 0xE0++0x03 hide.long 0x00 "SDIO_FIFO24,SDIO Data FIFO Register 24" in hgroup.long 0xE4++0x03 hide.long 0x00 "SDIO_FIFO25,SDIO Data FIFO Register 25" in hgroup.long 0xE8++0x03 hide.long 0x00 "SDIO_FIFO26,SDIO Data FIFO Register 26" in hgroup.long 0xEC++0x03 hide.long 0x00 "SDIO_FIFO27,SDIO Data FIFO Register 27" in hgroup.long 0xF0++0x03 hide.long 0x00 "SDIO_FIFO28,SDIO Data FIFO Register 28" in hgroup.long 0xF4++0x03 hide.long 0x00 "SDIO_FIFO29,SDIO Data FIFO Register 29" in hgroup.long 0xF8++0x03 hide.long 0x00 "SDIO_FIFO30,SDIO Data FIFO Register 30" in hgroup.long 0xFC++0x03 hide.long 0x00 "SDIO_FIFO31,SDIO Data FIFO Register 31" in width 0x0B tree.end endif sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")) tree.open "CAN (Controller Area Network)" tree "CAN 1" base ad:0x40006400 width 11. group.long 0x00++0x1F line.long 0x00 "CAN_MCR,CAN Master Control Register" bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen" bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset" bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled" bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled" bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once" bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked" bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order" textline " " bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode" bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize" line.long 0x04 "CAN_MSR,CAN Master Status Register" rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1" rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1" rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving" rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting" textline " " eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep" textline " " rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization" line.long 0x08 "CAN_TSR,CAN Transmit Status Register" rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest" rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest" rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest" rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty" textline " " rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty" rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty" rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3" bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort" textline " " eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error" eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost" eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful" eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed" textline " " bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort" eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error" eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost" eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful" textline " " eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed" bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort" eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error" eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost" textline " " eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful" eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed" line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register" bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release" eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun" eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full" rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3" line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register" bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release" eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun" eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full" rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3" line.long 0x14 "CAN_IER,CAN Interrupt Enable Register" bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled" line.long 0x18 "CAN_ESR,CAN Error Status Register" hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter" bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software" rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred" textline " " rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred" rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred" line.long 0x1C "CAN_BTR,CAN Bit Timing Register" bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent" bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3" bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler" tree "T0 Mailbox" if (((per.l((ad:0x40006400+0x180)))&0x4)==0x4) group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH0R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T1 Mailbox" if (((per.l((ad:0x40006400+0x190)))&0x4)==0x4) group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH1R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T2 Mailbox" if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x4) group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH2R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 0" if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4) rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1B0+0x04)++0x0B line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 1" if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4) rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1C0+0x04)++0x0B line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "Filter Registers" group.long 0x200++0x03 line.long 0x00 "CAN_FMR,CAN Filter Master Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*")&&!cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")||cpuis("STM32F103TB")||cpuis("STM32F7*")) hexmask.long.byte 0x00 8.--13. 1. " CAN2SB ,CAN2 start bank" bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active mode,Initialization" else sif (cpu()=="STM32F372CB")||(cpuis("STM32F446*"))||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F412*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H") hexmask.long.byte 0x00 8.--13. 1. " CANSB ,CAN start bank" textline " " endif bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active,Initialization" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01) group.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List" bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List" bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List" bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List" bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List" group.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single" group.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1" textline " " bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1" bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1" textline " " bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1" bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1" textline " " bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1" textline " " bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1" bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1" textline " " bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1" bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1" textline " " bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1" else rgroup.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List" bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List" bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List" bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List" bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List" bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List" bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List" bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List" bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List" bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List" textline " " endif bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List" bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List" bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List" rgroup.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit" textline " " endif bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single" rgroup.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1" bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1" bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1" textline " " bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1" bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1" bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1" textline " " bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1" bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1" bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1" textline " " bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1" bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1" bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1" textline " " bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1" bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1" textline " " endif bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1" textline " " bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1" bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1" textline " " bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1" bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1" textline " " bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1" endif group.long 0x21C++0x03 line.long 0x00 "CAN_FA1R,CAN Filter Activation Register" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) bitfld.long 0x00 27. " FACT27 ,Filter Active" "Not active,Active" bitfld.long 0x00 26. " FACT26 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 25. " FACT25 ,Filter Active" "Not active,Active" bitfld.long 0x00 24. " FACT24 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 23. " FACT23 ,Filter Active" "Not active,Active" bitfld.long 0x00 22. " FACT22 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 21. " FACT21 ,Filter Active" "Not active,Active" bitfld.long 0x00 20. " FACT20 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 19. " FACT19 ,Filter Active" "Not active,Active" bitfld.long 0x00 18. " FACT18 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 17. " FACT17 ,Filter Active" "Not active,Active" bitfld.long 0x00 16. " FACT16 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 15. " FACT15 ,Filter Active" "Not active,Active" bitfld.long 0x00 14. " FACT14 ,Filter Active" "Not active,Active" textline " " endif bitfld.long 0x00 13. " FACT13 ,Filter Active" "Not active,Active" bitfld.long 0x00 12. " FACT12 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 11. " FACT11 ,Filter Active" "Not active,Active" bitfld.long 0x00 10. " FACT10 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 9. " FACT9 ,Filter Active" "Not active,Active" bitfld.long 0x00 8. " FACT8 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 7. " FACT7 ,Filter Active" "Not active,Active" bitfld.long 0x00 6. " FACT6 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 5. " FACT5 ,Filter Active" "Not active,Active" bitfld.long 0x00 4. " FACT4 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 3. " FACT3 ,Filter Active" "Not active,Active" bitfld.long 0x00 2. " FACT2 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 1. " FACT1 ,Filter Active" "Not active,Active" bitfld.long 0x00 0. " FACT0 ,Filter Active" "Not active,Active" tree "Filter Bank Registers" sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00) group.long 0x240++0x03 line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x240++0x03 line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00) group.long 0x244++0x03 line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x244++0x03 line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00) group.long 0x248++0x03 line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x248++0x03 line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00) group.long 0x24C++0x03 line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x24C++0x03 line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00) group.long 0x250++0x03 line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x250++0x03 line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00) group.long 0x254++0x03 line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x254++0x03 line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00) group.long 0x258++0x03 line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x258++0x03 line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00) group.long 0x25C++0x03 line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x25C++0x03 line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00) group.long 0x260++0x03 line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x260++0x03 line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00) group.long 0x264++0x03 line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x264++0x03 line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00) group.long 0x268++0x03 line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x268++0x03 line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00) group.long 0x26C++0x03 line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x26C++0x03 line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00) group.long 0x270++0x03 line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x270++0x03 line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00) group.long 0x274++0x03 line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x274++0x03 line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00) group.long 0x278++0x03 line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x278++0x03 line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00) group.long 0x27C++0x03 line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x27C++0x03 line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00) group.long 0x280++0x03 line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x280++0x03 line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00) group.long 0x284++0x03 line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x284++0x03 line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00) group.long 0x288++0x03 line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x288++0x03 line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00) group.long 0x28C++0x03 line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x28C++0x03 line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00) group.long 0x290++0x03 line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x290++0x03 line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00) group.long 0x294++0x03 line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x294++0x03 line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00) group.long 0x298++0x03 line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x298++0x03 line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00) group.long 0x29C++0x03 line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x29C++0x03 line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00) group.long 0x2A0++0x03 line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A0++0x03 line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00) group.long 0x2A4++0x03 line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A4++0x03 line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00) group.long 0x2A8++0x03 line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A8++0x03 line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00) group.long 0x2AC++0x03 line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2AC++0x03 line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00) group.long 0x2B0++0x03 line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2B0++0x03 line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00) group.long 0x2B4++0x03 line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2B4++0x03 line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00) group.long 0x2B8++0x03 line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2B8++0x03 line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00) group.long 0x2BC++0x03 line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2BC++0x03 line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00) group.long 0x2C0++0x03 line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2C0++0x03 line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00) group.long 0x2C4++0x03 line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2C4++0x03 line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00) group.long 0x2C8++0x03 line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2C8++0x03 line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00) group.long 0x2CC++0x03 line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2CC++0x03 line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00) group.long 0x2D0++0x03 line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2D0++0x03 line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00) group.long 0x2D4++0x03 line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2D4++0x03 line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00) group.long 0x2D8++0x03 line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2D8++0x03 line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00) group.long 0x2DC++0x03 line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2DC++0x03 line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00) group.long 0x2E0++0x03 line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2E0++0x03 line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00) group.long 0x2E4++0x03 line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2E4++0x03 line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00) group.long 0x2E8++0x03 line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2E8++0x03 line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00) group.long 0x2EC++0x03 line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2EC++0x03 line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00) group.long 0x2F0++0x03 line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2F0++0x03 line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00) group.long 0x2F4++0x03 line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2F4++0x03 line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00) group.long 0x2F8++0x03 line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2F8++0x03 line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00) group.long 0x2FC++0x03 line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2FC++0x03 line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00) group.long 0x300++0x03 line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x300++0x03 line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00) group.long 0x304++0x03 line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x304++0x03 line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00) group.long 0x308++0x03 line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x308++0x03 line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00) group.long 0x30C++0x03 line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x30C++0x03 line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00) group.long 0x310++0x03 line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x310++0x03 line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00) group.long 0x314++0x03 line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x314++0x03 line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00) group.long 0x318++0x03 line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x318++0x03 line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00) group.long 0x31C++0x03 line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x31C++0x03 line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif elif cpuis("STM32F103*") if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00)) ; group.long 0x240++0x07 line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x240++0x07 line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00)) ; group.long 0x244++0x07 line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x244++0x07 line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00)) ; group.long 0x248++0x07 line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x248++0x07 line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00)) ; group.long 0x24C++0x07 line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x24C++0x07 line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00)) ; group.long 0x250++0x07 line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x250++0x07 line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00)) ; group.long 0x254++0x07 line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x254++0x07 line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00)) ; group.long 0x258++0x07 line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x258++0x07 line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00)) ; group.long 0x25C++0x07 line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x25C++0x07 line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00)) ; group.long 0x260++0x07 line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x260++0x07 line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00)) ; group.long 0x264++0x07 line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x264++0x07 line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00)) ; group.long 0x268++0x07 line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x268++0x07 line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00)) ; group.long 0x26C++0x07 line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x26C++0x07 line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00)) ; group.long 0x270++0x07 line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x270++0x07 line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00)) ; group.long 0x274++0x07 line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x274++0x07 line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)" bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif else group.long 0x240++0x03 line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x244++0x03 line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x248++0x03 line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x24C++0x03 line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x250++0x03 line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x254++0x03 line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x258++0x03 line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x25C++0x03 line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x260++0x03 line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x264++0x03 line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x268++0x03 line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x26C++0x03 line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x270++0x03 line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x274++0x03 line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x278++0x03 line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x27C++0x03 line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x280++0x03 line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x284++0x03 line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x288++0x03 line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x28C++0x03 line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x290++0x03 line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x294++0x03 line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x298++0x03 line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x29C++0x03 line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x2A0++0x03 line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x2A4++0x03 line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x2A8++0x03 line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" group.long 0x2AC++0x03 line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif tree.end tree.end width 0x0B tree.end tree "CAN 2" base ad:0x40006800 width 11. group.long 0x00++0x1F line.long 0x00 "CAN_MCR,CAN Master Control Register" bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen" bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset" bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled" bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled" bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once" bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked" bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order" textline " " bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode" bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize" line.long 0x04 "CAN_MSR,CAN Master Status Register" rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1" rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1" rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving" rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting" textline " " eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep" textline " " rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization" line.long 0x08 "CAN_TSR,CAN Transmit Status Register" rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest" rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest" rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest" rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty" textline " " rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty" rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty" rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3" bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort" textline " " eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error" eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost" eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful" eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed" textline " " bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort" eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error" eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost" eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful" textline " " eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed" bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort" eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error" eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost" textline " " eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful" eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed" line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register" bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release" eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun" eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full" rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3" line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register" bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release" eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun" eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full" rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3" line.long 0x14 "CAN_IER,CAN Interrupt Enable Register" bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled" line.long 0x18 "CAN_ESR,CAN Error Status Register" hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter" bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software" rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred" textline " " rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred" rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred" line.long 0x1C "CAN_BTR,CAN Bit Timing Register" bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent" bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3" bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler" tree "T0 Mailbox" if (((per.l((ad:0x40006800+0x180)))&0x4)==0x4) group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH0R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T1 Mailbox" if (((per.l((ad:0x40006800+0x190)))&0x4)==0x4) group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH1R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T2 Mailbox" if (((per.l((ad:0x40006800+0x1A0)))&0x4)==0x4) group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH2R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 0" if (((per.l((ad:0x40006800+0x1B0)))&0x4)==0x4) rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1B0+0x04)++0x0B line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 1" if (((per.l((ad:0x40006800+0x1C0)))&0x4)==0x4) rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1C0+0x04)++0x0B line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end width 0x0B tree.end sif cpuis("STM32F413*")||cpuis("STM32F423?H") tree "CAN 3" base ad:0x40006800 width 11. group.long 0x00++0x1F line.long 0x00 "CAN_MCR,CAN Master Control Register" bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen" bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset" bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled" bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled" bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once" bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked" bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order" textline " " bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode" bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize" line.long 0x04 "CAN_MSR,CAN Master Status Register" rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1" rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1" rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving" rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting" textline " " eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt" eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep" textline " " rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization" line.long 0x08 "CAN_TSR,CAN Transmit Status Register" rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest" rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest" rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest" rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty" textline " " rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty" rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty" rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3" bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort" textline " " eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error" eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost" eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful" eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed" textline " " bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort" eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error" eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost" eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful" textline " " eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed" bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort" eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error" eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost" textline " " eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful" eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed" line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register" bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release" eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun" eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full" rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3" line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register" bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release" eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun" eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full" rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3" line.long 0x14 "CAN_IER,CAN Interrupt Enable Register" bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled" line.long 0x18 "CAN_ESR,CAN Error Status Register" hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter" bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software" rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred" textline " " rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred" rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred" line.long 0x1C "CAN_BTR,CAN Bit Timing Register" bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent" bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3" bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler" tree "T0 Mailbox" if (((per.l((ad:0x40006C00+0x180)))&0x4)==0x4) group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x180++0x03 line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x180+0x04)++0x0B line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH0R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T1 Mailbox" if (((per.l((ad:0x40006C00+0x190)))&0x4)==0x4) group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x190++0x03 line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x190+0x04)++0x0B line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH1R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "T2 Mailbox" if (((per.l((ad:0x40006C00+0x1A0)))&0x4)==0x4) group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" else group.long 0x1A0++0x03 line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested" endif group.long (0x1A0+0x04)++0x0B line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_TDH2R,Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 0" if (((per.l((ad:0x40006C00+0x1B0)))&0x4)==0x4) rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1B0++0x03 line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1B0+0x04)++0x0B line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "FIFO 1" if (((per.l((ad:0x40006C00+0x1C0)))&0x4)==0x4) rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" else rgroup.long 0x1C0++0x03 line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register" hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier" bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" textline " " bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote" endif rgroup.long (0x1C0+0x04)++0x0B line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register" hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp" hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index" textline " " bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..." line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register" hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3" hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2" hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1" hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0" line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register" hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7" hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6" hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5" hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4" tree.end tree "Filter Registers" group.long 0x200++0x03 line.long 0x00 "CAN_FMR,CAN Filter Master Register" bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active,Initialization" if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01) group.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List" bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List" bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List" group.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single" group.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1" textline " " bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1" bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1" textline " " bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1" bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1" textline " " bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1" else rgroup.long 0x204++0x03 line.long 0x00 "CAN_FM1R,CAN Filter Mode Register" bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List" bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List" bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List" bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List" bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List" bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List" bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List" bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List" bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List" textline " " bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List" bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List" rgroup.long 0x20C++0x03 line.long 0x00 "CAN_FS1R,CAN Filter Scale Register" bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single" textline " " bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single" bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single" rgroup.long 0x214++0x03 line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register" bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1" bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1" bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1" textline " " bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1" bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1" bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1" textline " " bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1" bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1" bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1" textline " " bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1" bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1" bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1" textline " " bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1" bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1" endif group.long 0x21C++0x03 line.long 0x00 "CAN_FA1R,CAN Filter Activation Register" bitfld.long 0x00 13. " FACT13 ,Filter Active" "Not active,Active" bitfld.long 0x00 12. " FACT12 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 11. " FACT11 ,Filter Active" "Not active,Active" bitfld.long 0x00 10. " FACT10 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 9. " FACT9 ,Filter Active" "Not active,Active" bitfld.long 0x00 8. " FACT8 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 7. " FACT7 ,Filter Active" "Not active,Active" bitfld.long 0x00 6. " FACT6 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 5. " FACT5 ,Filter Active" "Not active,Active" bitfld.long 0x00 4. " FACT4 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 3. " FACT3 ,Filter Active" "Not active,Active" bitfld.long 0x00 2. " FACT2 ,Filter Active" "Not active,Active" textline " " bitfld.long 0x00 1. " FACT1 ,Filter Active" "Not active,Active" bitfld.long 0x00 0. " FACT0 ,Filter Active" "Not active,Active" tree "Filter Bank Registers" if (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*")) if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<0.))==0x00) group.long 0x240++0x03 line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x240++0x03 line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<0.))==0x00) group.long 0x244++0x03 line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x244++0x03 line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<1.))==0x00) group.long 0x248++0x03 line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x248++0x03 line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<1.))==0x00) group.long 0x24C++0x03 line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x24C++0x03 line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<2.))==0x00) group.long 0x250++0x03 line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x250++0x03 line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<2.))==0x00) group.long 0x254++0x03 line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x254++0x03 line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<3.))==0x00) group.long 0x258++0x03 line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x258++0x03 line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<3.))==0x00) group.long 0x25C++0x03 line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x25C++0x03 line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<4.))==0x00) group.long 0x260++0x03 line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x260++0x03 line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<4.))==0x00) group.long 0x264++0x03 line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x264++0x03 line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<5.))==0x00) group.long 0x268++0x03 line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x268++0x03 line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<5.))==0x00) group.long 0x26C++0x03 line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x26C++0x03 line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<6.))==0x00) group.long 0x270++0x03 line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x270++0x03 line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<6.))==0x00) group.long 0x274++0x03 line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x274++0x03 line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<7.))==0x00) group.long 0x278++0x03 line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x278++0x03 line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<7.))==0x00) group.long 0x27C++0x03 line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x27C++0x03 line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<8.))==0x00) group.long 0x280++0x03 line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x280++0x03 line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<8.))==0x00) group.long 0x284++0x03 line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x284++0x03 line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<9.))==0x00) group.long 0x288++0x03 line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x288++0x03 line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<9.))==0x00) group.long 0x28C++0x03 line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x28C++0x03 line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<10.))==0x00) group.long 0x290++0x03 line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x290++0x03 line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<10.))==0x00) group.long 0x294++0x03 line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x294++0x03 line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<11.))==0x00) group.long 0x298++0x03 line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x298++0x03 line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<11.))==0x00) group.long 0x29C++0x03 line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x29C++0x03 line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<12.))==0x00) group.long 0x2A0++0x03 line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A0++0x03 line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<12.))==0x00) group.long 0x2A4++0x03 line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A4++0x03 line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<13.))==0x00) group.long 0x2A8++0x03 line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2A8++0x03 line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif if (((per.l(ad:0x40006C00+0x200))&0x01)==0x01)||(((per.l(ad:0x40006C00+0x21C))&(0x01<<13.))==0x00) group.long 0x2AC++0x03 line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" else rgroup.long 0x2AC++0x03 line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)" bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched" textline " " bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched" bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched" endif endif tree.end tree.end width 0x0B tree.end endif tree.end endif tree "USB_OTG_FS (USB On-the-go Full-speed)" base ad:0x50000000 width 17. tree "OTG_FS Global Registers" if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1) group.long 0x00++0x1B line.long 0x00 "OTG_FS_GOTGCTL,OTG_FS Control And Status Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 20. " OTGVER ,OTG version" "ver 1.3,ver 2.0" textline " " endif rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Not valid,Valid" rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short" textline " " rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "0,1" bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "0,1" bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled" endif line.long 0x04 "OTG_FS_GOTGINT,OTG_FS Interrupt Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed" textline " " endif eventfld.long 0x04 19. " DBCDNE ,Debounce done" "Not done,Done" eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed" textline " " eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected" eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed" textline " " eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed" eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected" line.long 0x08 "OTG_FS_GAHBCFG,OTG_FS AHB Configuration Register" bitfld.long 0x08 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty" textline " " sif (cpu()=="STM32F4*") bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty" textline " " endif bitfld.long 0x08 0. " GINT ,Global interrupt mask" "Masked,Unmasked" line.long 0x0C "OTG_FS_GUSBCFG,OTG_FS USB Configuration Register" sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High" textline " " endif bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced" textline " " bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced" textline " " bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled" bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled" textline " " sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x0C 6. " PHYSEL ,Full Speed serial transceiver select" "0,1" textline " " endif bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_FS_GRSTCTL,OTG_FS Reset Register" rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic,Periodic,,,,,,,,,,,,,,,All,?..." else bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic,Periodic,2,3,4,5,6,7,8,9,10,11,12,13,14,15,All,?..." endif textline " " bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit" bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High" textline " " bitfld.long 0x10 2. " FCRST ,Host frame counter reset" "No reset,Reset" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset" else bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset" endif textline " " bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset" line.long 0x14 "OTG_FS_GINTSTS,OTG_FS Core Interrupt Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode" else bitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode" endif eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "Not occurred,Occurred" endif textline " " rbitfld.long 0x14 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x14 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt" rbitfld.long 0x14 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt" sif (cpuis("STM32F4*"))||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x14 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty" endif textline " " rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty" textline " " eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started" rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" textline " " line.long 0x18 "OTG_FS_GINTMSK,OTG_FS Interrupt Mask Register" bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" textline " " sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" else bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" endif textline " " sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x18 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked" textline " " endif bitfld.long 0x18 26. " PTXFEM ,Periodic TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x18 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked" textline " " rbitfld.long 0x18 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked" bitfld.long 0x18 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked" textline " " bitfld.long 0x18 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" textline " " bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked" bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" textline " " rgroup.long 0x1C++0x07 line.long 0x00 "OTG_FS_GRXSTSR,OTG_FS Receive Status Debug Read Register" bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..." sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,?..." else bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA" endif textline " " hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x20++0x03 hide.long 0x00 "OTG_FS_GRXSTSP,OTG Status Read And Pop Register" in else group.long 0x00++0x1B line.long 0x00 "OTG_FS_GOTGCTL,OTG_FS Control And Status Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 20. " OTGVER ,OTG version" "ver 1.3,ver 2.0" textline " " endif rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Not valid,Valid" rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device" textline " " sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled" bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested" textline " " rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Successful" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "0,1" textline " " bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled" endif bitfld.long 0x00 1. " SRQ ,Session request" "Not requested,Requested" textline " " rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Successful" line.long 0x04 "OTG_FS_GOTGINT,OTG_FS Interrupt Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed" textline " " endif eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed" eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected" textline " " eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed" eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed" textline " " eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected" line.long 0x08 "OTG_FS_GAHBCFG,OTG_FS AHB Configuration Register" bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty" bitfld.long 0x08 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked" line.long 0x0C "OTG_FS_GUSBCFG,OTG_FS USB Configuration Register" sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High" textline " " endif bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced" textline " " bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced" sif (!cpuis("STM32F2*")&&!cpuis("STM32F4*")) textline " " bitfld.long 0x0C 14. " NPTXRWEN , non-periodic TxFIFO rewind enable" "Disabled,Enabled" endif textline " " bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled" textline " " sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x0C 6. " PHYSEL ,Full Speed serial transceiver select" "0,1" textline " " endif bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_FS_GRSTCTL,OTG_FS Reset Register" rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High" bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit" bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset" else bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset" endif textline " " bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset" line.long 0x14 "OTG_FS_GINTSTS,OTG_FS Core Interrupt Register" rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode" eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "Not occurred,Occurred" endif sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " eventfld.long 0x14 23. " RSTDET ,Reset detected interrupt" "No interrupt,Interrupt" endif textline " " eventfld.long 0x14 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No interrupt,Interrupt" eventfld.long 0x14 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x14 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt" eventfld.long 0x14 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 13. " ENUMDNE ,Enumeration done" "Not done,Done" eventfld.long 0x14 12. " USBRST ,USB reset" "No reset,Reset" textline " " eventfld.long 0x14 11. " USBSUSP ,USB suspend" "Not suspended,Suspended" eventfld.long 0x14 10. " ESUSP ,Early suspend" "Not suspended,Suspended" textline " " rbitfld.long 0x14 7. " GONAKEFF ,Global OUT NAK effective" "Low,High" rbitfld.long 0x14 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High" textline " " rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty" eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started" textline " " rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" line.long 0x18 "OTG_FS_GINTMSK,OTG_FS Interrupt Mask Register" bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" textline " " sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x18 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked" textline " " endif sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x18 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked" elif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked" else bitfld.long 0x18 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 22. " FSUSPM ,Data fetch suspended mask" "Masked,Unmasked" bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked" endif textline " " bitfld.long 0x18 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked" bitfld.long 0x18 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked" sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") textline " " bitfld.long 0x18 17. " EPMISM ,Endpoint mismatch interrupt mask" "Masked,Unmasked" endif textline " " bitfld.long 0x18 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked" bitfld.long 0x18 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked" bitfld.long 0x18 12. " USBRST ,USB reset mask" "Masked,Unmasked" textline " " bitfld.long 0x18 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked" bitfld.long 0x18 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked" textline " " bitfld.long 0x18 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked" bitfld.long 0x18 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked" textline " " sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" else bitfld.long 0x18 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" endif textline " " bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked" bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" rgroup.long 0x1C++0x03 line.long 0x00 "OTG_FS_GRXSTSR,OTG_FS Receive Status Debug Read Register" bitfld.long 0x00 21.--24. " FRMNUM ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F412*") bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP ransaction completed,,SETUP data packet received,?..." else bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,Transaction completed,,SETUP data packet received,?..." endif textline " " sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,?..." else bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA" endif hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" textline " " bitfld.long 0x00 0.--3. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x20++0x03 hide.long 0x00 "OTG_FS_GRXSTSP,OTG Status Read And Pop Register" in endif group.long 0x24++0x03 line.long 0x00 "OTG_FS_GRXFSIZ,OTG_FS Receive FIFO Size Register" hexmask.long.word 0x00 0.--15. 1. " RXFD ,RxFIFO depth" if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1) group.long 0x28++0x3 line.long 0x00 "OTG_FS_HNPTXFSIZ,OTG_FS Host Non-periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " NPTXFSA ,Non-periodic transmit RAM start address" rgroup.long 0x2C++0x03 line.long 0x00 "OTG_FS_HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/queue Status Register" bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue - CH/EP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,,Channel halt" textline " " bitfld.long 0x00 24. " NPTXQTOP[24] ,Top of the nonperiodic transmit request queue" "Not terminated,Terminated" textline " " hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available" else group.long 0x28++0x3 line.long 0x00 "OTG_FS_DIEPTXF0,Endpoint 0 Transmit FIFO Size" hexmask.long.word 0x00 16.--31. 1. " TX0FD ,Endpoint 0 TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Endpoint 0 transmit RAM start address" hgroup.long 0x2C++0x03 hide.long 0x00 "OTG_FS_HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/queue Status Register" endif group.long 0x38++0x07 line.long 0x00 "OTG_FS_GCCFG,OTG_FS General Core Configuration Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 21. " VBDEM ,USB VBUS detection enable" "Disabled,Enabled" bitfld.long 0x00 20. " SDEN ,Secondary detection mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PDEN ,Primary detection mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DCDEN ,Data contact detection mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " BCDEN ,Battery charging detector enable" "Disabled,Enabled" textline " " elif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled" textline " " else sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x00 21. " NOVBUSSENS ,VBUS sensing disable" "No,Yes" textline " " endif bitfld.long 0x00 20. " SOFOUTEN ,SOF output enable" "Disabled,Enabled" bitfld.long 0x00 19. " VBUSBSEN ,Enable the VBUS sensing B device" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " VBUSASEN ,Enable the VBUS sensing A device" "Disabled,Enabled" textline " " endif sif (cpuis("STM32F2*")) bitfld.long 0x00 16. " PWRDWN ,Power down" "Not active,Active" else bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down" endif sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") textline " " bitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal,PS2/proprietary" bitfld.long 0x00 2. " SDET ,Secondary detection status" "CDP,DCP" textline " " bitfld.long 0x00 1. " PDET ,Primary detection status" "Not detected,Detected" bitfld.long 0x00 0. " DCDET ,Data contact detection" "Not detected,Detected" endif line.long 0x04 "OTG_FS_CID,OTG_FS Core ID Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1) group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Sending,Cleared" bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM Channel Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes" textline " " rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1" rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..." textline " " bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled" bitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1" textline " " bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000" bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" textline " " else group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes" textline " " rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1" rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..." textline " " bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled" rbitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1" textline " " rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000" bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" textline " " endif endif group.long 0x100++0x03 line.long 0x00 "OTG_FS_HPTXFSIZ,OTG_FS Host Periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " PTXFSIZ ,Host periodic TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " PTXSA ,Host periodic TxFIFO start address" sif (cpuis("STM32F2*")||cpuis("STM32F4*")&&!cpuis("STM32F446*")&&!cpuis("STM32F412*")) group.long 0x104++0x03 line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" elif cpuis("STM32F446*")||cpuis("STM32F412*") group.long 0x104++0x03 line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x110++0x03 line.long 0x00 "OTG_FS_DIEPTXF4,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x114++0x03 line.long 0x00 "OTG_FS_DIEPTXF5,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" else group.long 0x104++0x03 line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" group.long 0x110++0x03 line.long 0x00 "OTG_FS_DIEPTXF4,OTG_FS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address" endif tree.end tree "Host mode registers" if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1) group.long 0x400++0x07 line.long 0x00 "OTG_FS_HCFG,OTG_FS Host Configuration Register" rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported" bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz,?..." line.long 0x04 "OTG_FS_HFIR,OTG_FS Host Frame Interval Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 16. " RLDCTRL ,Reload control" "Cannot reload,Can Reload" textline " " endif hexmask.long.word 0x04 0.--15. 1. " FRIVL ,Frame interval" rgroup.long 0x408++0x03 line.long 0x00 "OTG_FS_HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register" hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining" hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number" rgroup.long 0x410++0x03 line.long 0x00 "OTG_FS_HPTXSTS,OTG_FS_Host Periodic Transmit FIFO/Queue Status Register" hexmask.long.byte 0x00 24.--31. 1. " PTXQTOP ,Top of the periodic transmit request queue" hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available" textline " " hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available" rgroup.long 0x414++0x03 line.long 0x00 "OTG_FS_HAINT,OTG_FS Host All Channels Interrupt Register" sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x00 15. " HAINT[15] ,Channel 15 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " HAINT[14] ,Channel 14 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " HAINT[13] ,Channel 13 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " HAINT[12] ,Channel 12 interrupt" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 11. " HAINT[11] ,Channel 11 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " HAINT[10] ,Channel 10 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " HAINT[9] ,Channel 9 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " HAINT[8] ,Channel 8 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " HAINT[7] ,Channel 7 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " HAINT[6] ,Channel 6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " HAINT[5] ,Channel 5 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 4. " HAINT[4] ,Channel 4 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " HAINT[3] ,Channel 3 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " HAINT[2] ,Channel 2 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " HAINT[1] ,Channel 1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " HAINT[0] ,Channel 0 interrupt" "No interrupt,Interrupt" group.long 0x418++0x03 line.long 0x00 "OTG_FS_HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register" sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x00 15. " HAINTM[15] ,Channel interrupt mask 15" "Masked,Unmasked" bitfld.long 0x00 14. " HAINTM[14] ,Channel interrupt mask 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " HAINTM[13] ,Channel interrupt mask 13" "Masked,Unmasked" bitfld.long 0x00 12. " HAINTM[12] ,Channel interrupt mask 12" "Masked,Unmasked" textline " " endif bitfld.long 0x00 11. " HAINTM[11] ,Channel interrupt mask 11" "Masked,Unmasked" bitfld.long 0x00 10. " HAINTM[10] ,Channel interrupt mask 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " HAINTM[9] ,Channel interrupt mask 9" "Masked,Unmasked" bitfld.long 0x00 8. " HAINTM[8] ,Channel interrupt mask 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " HAINTM[7] ,Channel interrupt mask 7" "Masked,Unmasked" bitfld.long 0x00 6. " HAINTM[6] ,Channel interrupt mask 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " HAINTM[5] ,Channel interrupt mask 5" "Masked,Unmasked" bitfld.long 0x00 4. " HAINTM[4] ,Channel interrupt mask 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " HAINTM[3] ,Channel interrupt mask 3" "Masked,Unmasked" bitfld.long 0x00 2. " HAINTM[2] ,Channel interrupt mask 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " HAINTM[1] ,Channel interrupt mask 1" "Masked,Unmasked" bitfld.long 0x00 0. " HAINTM[0] ,Channel interrupt mask 0" "Masked,Unmasked" group.long 0x440++0x03 line.long 0x00 "OTG_FS_HPRT,OTG_FS Host Port Control And Status Register" rbitfld.long 0x00 17.--18. " PSPD ,Port speed" ",Full,Low,?..." bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..." textline " " bitfld.long 0x00 12. " PPWR ,Port power" "Off,On" rbitfld.long 0x00 11. " PLSTS[1] ,Port line status (Logic level of OTG_FS_FS_DP)" "Low,High" textline " " rbitfld.long 0x00 10. " PLSTS[0] ,Port line status (Logic level of OTG_FS_FS_DM)" "Low,High" bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed" rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active" textline " " eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled" else bitfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled" endif textline " " eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected" rbitfld.long 0x00 0. " PCSTS ,Port connect status" "Not device,Device" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x500++0x03 line.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x500+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x520++0x03 line.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x520+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x540++0x03 line.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x540+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x560++0x03 line.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x560+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x580++0x03 line.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x580+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5A0++0x03 line.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5A0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5C0++0x03 line.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5C0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5E0++0x03 line.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5E0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x600++0x03 line.long 0x00 "OTG_FS_HCCHAR8,OTG_FS Host Channel-8 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x600+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT8,OTG_FS Host Channel-8 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x620++0x03 line.long 0x00 "OTG_FS_HCCHAR9,OTG_FS Host Channel-9 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x620+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT9,OTG_FS Host Channel-9 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x640++0x03 line.long 0x00 "OTG_FS_HCCHAR10,OTG_FS Host Channel-10 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x640+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT10,OTG_FS Host Channel-10 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x660++0x03 line.long 0x00 "OTG_FS_HCCHAR11,OTG_FS Host Channel-11 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x660+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT11,OTG_FS Host Channel-11 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-" else bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0x500++0x03 line.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x500+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x520++0x03 line.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x520+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x540++0x03 line.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x540+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x560++0x03 line.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x560+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x580++0x03 line.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x580+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5A0++0x03 line.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5A0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5C0++0x03 line.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5C0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x5E0++0x03 line.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed" textline " " bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" group.long (0x5E0+0x08)++0x0B line.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register" eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x04 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register" bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked" bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x08 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register" bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size" endif else hgroup.long 0x400++0x03 hide.long 0x00 "OTG_FS_HCFG,OTG_FS Host Configuration Register" hgroup.long 0x404++0x03 hide.long 0x00 "OTG_FS_HFIR,OTG_FS Host Frame Interval Register" hgroup.long 0x408++0x03 hide.long 0x00 "OTG_FS_HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register" hgroup.long 0x410++0x03 hide.long 0x00 "OTG_FS_HPTXSTS,OTG_FS_Host Periodic Transmit FIFO/Queue Status Register" hgroup.long 0x414++0x03 hide.long 0x00 "OTG_FS_HAINT,OTG_FS Host All Channels Interrupt Register" hgroup.long 0x418++0x03 hide.long 0x00 "OTG_FS_HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register" hgroup.long 0x440++0x03 hide.long 0x00 "OTG_FS_HPRT,OTG_FS Host Port Control And Status Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") hgroup.long 0x500++0x03 hide.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register" hgroup.long 0x520++0x03 hide.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register" hgroup.long (0x520+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register" hgroup.long (0x520+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register" hgroup.long (0x520+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register" hgroup.long 0x540++0x03 hide.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register" hgroup.long 0x560++0x03 hide.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register" hgroup.long (0x560+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register" hgroup.long (0x560+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register" hgroup.long (0x560+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register" hgroup.long 0x580++0x03 hide.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register" hgroup.long 0x5A0++0x03 hide.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register" hgroup.long (0x5A0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register" hgroup.long (0x5A0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register" hgroup.long (0x5A0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register" hgroup.long 0x5C0++0x03 hide.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register" hgroup.long 0x5E0++0x03 hide.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register" hgroup.long (0x5E0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register" hgroup.long (0x5E0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register" hgroup.long (0x5E0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register" hgroup.long 0x600++0x03 hide.long 0x00 "OTG_FS_HCCHAR8,OTG_FS Host Channel-8 Characteristics Register" hgroup.long (0x600+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT8,OTG_FS Host Channel-8 Interrupt Register" hgroup.long (0x600+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register" hgroup.long (0x600+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register" hgroup.long 0x620++0x03 hide.long 0x00 "OTG_FS_HCCHAR9,OTG_FS Host Channel-9 Characteristics Register" hgroup.long (0x620+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT9,OTG_FS Host Channel-9 Interrupt Register" hgroup.long (0x620+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register" hgroup.long (0x620+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register" hgroup.long 0x640++0x03 hide.long 0x00 "OTG_FS_HCCHAR10,OTG_FS Host Channel-10 Characteristics Register" hgroup.long (0x640+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT10,OTG_FS Host Channel-10 Interrupt Register" hgroup.long (0x640+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register" hgroup.long (0x640+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register" hgroup.long 0x660++0x03 hide.long 0x00 "OTG_FS_HCCHAR11,OTG_FS Host Channel-11 Characteristics Register" hgroup.long (0x660+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT11,OTG_FS Host Channel-11 Interrupt Register" hgroup.long (0x660+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register" hgroup.long (0x660+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register" else hgroup.long 0x500++0x03 hide.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register" hgroup.long 0x520++0x03 hide.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register" hgroup.long (0x520+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register" hgroup.long (0x520+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register" hgroup.long (0x520+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register" hgroup.long 0x540++0x03 hide.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register" hgroup.long 0x560++0x03 hide.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register" hgroup.long (0x560+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register" hgroup.long (0x560+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register" hgroup.long (0x560+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register" hgroup.long 0x580++0x03 hide.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register" hgroup.long 0x5A0++0x03 hide.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register" hgroup.long (0x5A0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register" hgroup.long (0x5A0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register" hgroup.long (0x5A0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register" hgroup.long 0x5C0++0x03 hide.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register" hgroup.long 0x5E0++0x03 hide.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register" hgroup.long (0x5E0+0x08)++0x03 hide.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register" hgroup.long (0x5E0+0x0C)++0x03 hide.long 0x00 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register" hgroup.long (0x5E0+0x10)++0x03 hide.long 0x00 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register" endif endif tree.end width 19. tree "Device mode registers" group.long 0x800++0x07 line.long 0x00 "OTG_FS_DCFG,OTG_FS Device Configuration Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Not masked,Masked" textline " " endif bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%" hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address" textline " " bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "NAK and STALL,STALL" bitfld.long 0x00 0.--1. " DSPD ,Device speed" ",,,Full" line.long 0x04 "OTG_FS_DCTL,OTG_FS Device Control Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected" textline " " endif bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done" "Not done,Done" bitfld.long 0x04 10. " CGONAK ,Clear global OUT NAK" "No effect,Clear" textline " " bitfld.long 0x04 9. " SGONAK ,Set global OUT NAK" "No effect,Set" bitfld.long 0x04 8. " CGINAK ,Clear global IN NAK" "No effect,Clear" textline " " bitfld.long 0x04 7. " SGINAK ,Set global IN NAK" "No effect,Set" bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..." textline " " rbitfld.long 0x04 3. " GONSTS ,Global OUT NAK status" "Sent NAK and STALL,Sent a NAK" textline " " rbitfld.long 0x04 2. " GINSTS ,Global IN NAK status" "Data availability,Non-periodic IN endpoints" textline " " bitfld.long 0x04 1. " SDIS ,Soft disconnect" "Connected,Not connected" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "No effect,Wakeup" else bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "Suspended,Not suspended" endif rgroup.long 0x808++0x03 line.long 0x00 "OTG_FS_DSTS,OTG_FS Device Status Register" sif cpuis("STM32F446*") bitfld.long 0x00 23. " DEVLNSTS ,Device line status" "0,1" bitfld.long 0x00 22. " DEVLNSTS ,Device line status" "0,1" textline " " elif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 23. " DEVLNSTS_D+ ,Device line status - logic level of D+" "Low,High" bitfld.long 0x00 22. " DEVLNSTS_D- ,Device line status - logic level of D+" "Low,High" textline " " endif hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF" bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error" textline " " bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full" bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended" group.long 0x810++0x07 line.long 0x00 "OTG_FS_DIEPMSK,OTG_FS Device IN Endpoint Common Interrupt Mask Register" sif ((!cpuis("STM32F2*"))&&(!cpuis("STM32F4*"))) bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked" bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked" textline " " endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked" textline " " endif bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked" bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked" textline " " bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x00 3. " TOM ,Timeout condition mask" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" line.long 0x04 "OTG_FS_DOEPMSK,OTG_FS Device OUT Endpoint Common Interrupt Mask Register" sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked" else bitfld.long 0x04 9. " BOIM ,BNA interrupt mask" "Masked,Unmasked" bitfld.long 0x04 8. " OPEM ,OUT packet error mask" "Masked,Unmasked" textline " " bitfld.long 0x04 6. " B2BSTUP ,Back-to-back SETUP packets received mask" "Masked,Unmasked" bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked" endif textline " " bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked" bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" rgroup.long 0x818++0x03 line.long 0x00 "OTG_FS_DAINT,OTG_FS Device All Endpoints Interrupt Register" bitfld.long 0x00 31. " OUTEPINT[15] ,OUT endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 30. " OUTEPINT[14] ,OUT endpoint interrupt bit 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " OUTEPINT[13] ,OUT endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 28. " OUTEPINT[12] ,OUT endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " OUTEPINT[11] ,OUT endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 26. " OUTEPINT[10] ,OUT endpoint interrupt bit 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " OUTEPINT[9] ,OUT endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 24. " OUTEPINT[8] ,OUT endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " OUTEPINT[7] ,OUT endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 22. " OUTEPINT[6] ,OUT endpoint interrupt bit 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " OUTEPINT[5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 20. " OUTEPINT[4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " OUTEPINT[3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 18. " OUTEPINT[2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " OUTEPINT[1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 16. " OUTEPINT[0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INEPINT[15] ,IN endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " INEPINT[14] ,IN endpoint interrupt bit 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INEPINT[13] ,IN endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " INEPINT[12] ,IN endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INEPINT[11] ,IN endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " INEPINT[10] ,IN endpoint interrupt bit 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INEPINT[9] ,IN endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " INEPINT[8] ,IN endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INEPINT[7] ,IN endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " INEPINT[6] ,IN endpoint interrupt bit 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INEPINT[5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " INEPINT[4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INEPINT[3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " INEPINT[2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INEPINT[1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " INEPINT[0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt" group.long 0x81C++0x03 line.long 0x00 "OTG_FS_DAINTMSK,OTG_FS All Endpoints Interrupt Mask Register" bitfld.long 0x00 31. " OEPM[15] ,OUT EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 30. " OEPM[14] ,OUT EP interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 29. " OEPM[13] ,OUT EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 28. " OEPM[12] ,OUT EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " OEPM[11] ,OUT EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 26. " OEPM[10] ,OUT EP interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 25. " OEPM[9] ,OUT EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 24. " OEPM[8] ,OUT EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 23. " OEPM[7] ,OUT EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 22. " OEPM[6] ,OUT EP interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 21. " OEPM[5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 20. " OEPM[4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 19. " OEPM[3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 18. " OEPM[2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 17. " OEPM[1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 16. " OEPM[0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked" textline " " bitfld.long 0x00 15. " IEPM[15] ,IN EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " IEPM[14] ,IN EP interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " IEPM[13] ,IN EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " IEPM[12] ,IN EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " IEPM[11] ,IN EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " IEPM[10] ,IN EP interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " IEPM[9] ,IN EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " IEPM[8] ,IN EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " IEPM[7] ,IN EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " IEPM[6] ,IN EP interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " IEPM[5] ,IN EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " IEPM[4] ,IN EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " IEPM[3] ,IN EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " IEPM[2] ,IN EP interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " IEPM[1] ,IN EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " IEPM[0] ,IN EP interrupt mask bit 0" "Masked,Unmasked" group.long 0x828++0x07 line.long 0x00 "OTG_FS_DVBUSDIS,OTG_FS Device VBUS Discharge Time Register" hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time" line.long 0x04 "OTG_FS_DVBUSPULSE,OTG_FS device VBUS Pulsing Time Register" hexmask.long.word 0x04 0.--11. 1. " DVBUSP ,Device VBUS pulsing time" group.long 0x834++0x03 line.long 0x00 "OTG_FS_DIEPEMPMSK,OTG_FS Device IN Endpoint FIFO Empty Interrupt Mask Register" bitfld.long 0x00 15. " INEPTXFEM[15] ,IN EP Tx FIFO empty interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " INEPTXFEM[14] ,IN EP Tx FIFO empty interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " INEPTXFEM[13] ,IN EP Tx FIFO empty interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " INEPTXFEM[12] ,IN EP Tx FIFO empty interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " INEPTXFEM[11] ,IN EP Tx FIFO empty interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " INEPTXFEM[10] ,IN EP Tx FIFO empty interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " INEPTXFEM[9] ,IN EP Tx FIFO empty interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " INEPTXFEM[8] ,IN EP Tx FIFO empty interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " INEPTXFEM[7] ,IN EP Tx FIFO empty interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " INEPTXFEM[6] ,IN EP Tx FIFO empty interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " INEPTXFEM[5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " INEPTXFEM[4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " INEPTXFEM[3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " INEPTXFEM[2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " INEPTXFEM[1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " INEPTXFEM[0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked" group.long 0x900++0x03 line.long 0x00 "OTG_FS_DIEPCTL0,OTG_FS Device Control IN endpoint 0 Control Register" rbitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "Not received,Received" textline " " rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK,NAK" textline " " rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x50000000+0x920))&0xC0000)==0x40000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0x80000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0xC0000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x940))&0xC0000)==0x40000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0x80000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0xC0000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x960))&0xC0000)==0x40000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0x80000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0xC0000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x980))&0xC0000)==0x40000) group.long 0x980++0x03 line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0x80000) group.long 0x980++0x03 line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0xC0000) group.long 0x980++0x03 line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x980++0x03 line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x40000) group.long 0x9A0++0x03 line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x80000) group.long 0x9A0++0x03 line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0xC0000) group.long 0x9A0++0x03 line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9A0++0x03 line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif else if (((per.l(ad:0x50000000+0x920))&0xC0000)==0x40000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0x80000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0xC0000) group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x920++0x03 line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x940))&0xC0000)==0x40000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0x80000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0xC0000) group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x940++0x03 line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0x960))&0xC0000)==0x40000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0x80000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0xC0000) group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x960++0x03 line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" endif textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif group.long 0xB00++0x03 line.long 0x00 "OTG_FS_DOEPCTL0,OTG_FS Device Control OUT Endpoint 0 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x40000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x80000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0xC0000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x40000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x80000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0xC0000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x40000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x80000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0xC0000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x40000) group.long 0xB80++0x03 line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x80000) group.long 0xB80++0x03 line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0xC0000) group.long 0xB80++0x03 line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB80++0x03 line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x40000) group.long 0xBA0++0x03 line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x80000) group.long 0xBA0++0x03 line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0xC0000) group.long 0xBA0++0x03 line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBA0++0x03 line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif else if (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x40000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x80000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0xC0000) group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB20++0x03 line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x40000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x80000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0xC0000) group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB40++0x03 line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x40000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x80000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0xC0000) group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB60++0x03 line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x908++0x03 line.long 0x00 "OTG_FS_DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x928++0x03 line.long 0x00 "OTG_FS_DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x948++0x03 line.long 0x00 "OTG_FS_DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x968++0x03 line.long 0x00 "OTG_FS_DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x988++0x03 line.long 0x00 "OTG_FS_DIEPINT4,OTG_FS Device Endpoint-4 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9A8++0x03 line.long 0x00 "OTG_FS_DIEPINT5,OTG_FS Device Endpoint-5 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" else eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" endif textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0x908++0x03 line.long 0x00 "OTG_FS_DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x928++0x03 line.long 0x00 "OTG_FS_DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x948++0x03 line.long 0x00 "OTG_FS_DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x968++0x03 line.long 0x00 "OTG_FS_DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") if ((per.l(ad:0x50000000+0xB08-0x08)&0xC0000)==0x00) group.long 0xB08++0x03 line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB08++0x03 line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x50000000+0xB28-0x08)&0xC0000)==0x00) group.long 0xB28++0x03 line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB28++0x03 line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x50000000+0xB48-0x08)&0xC0000)==0x00) group.long 0xB48++0x03 line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB48++0x03 line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x50000000+0xB68-0x08)&0xC0000)==0x00) group.long 0xB68++0x03 line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB68++0x03 line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x50000000+0xB88-0x08)&0xC0000)==0x00) group.long 0xB88++0x03 line.long 0x00 "OTG_FS_DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB88++0x03 line.long 0x00 "OTG_FS_DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x50000000+0xBA8-0x08)&0xC0000)==0x00) group.long 0xBA8++0x03 line.long 0x00 "OTG_FS_DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBA8++0x03 line.long 0x00 "OTG_FS_DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif else sif (!cpuis("STM32F4*")) group.long 0xB08++0x03 line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else if ((per.l(ad:0x50000000+0xB08-0x08)&0xC0000)==0x00) group.long 0xB08++0x03 line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB08++0x03 line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif endif sif (!cpuis("STM32F4*")) group.long 0xB28++0x03 line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else if ((per.l(ad:0x50000000+0xB28-0x08)&0xC0000)==0x00) group.long 0xB28++0x03 line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB28++0x03 line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif endif sif (!cpuis("STM32F4*")) group.long 0xB48++0x03 line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else if ((per.l(ad:0x50000000+0xB48-0x08)&0xC0000)==0x00) group.long 0xB48++0x03 line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB48++0x03 line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif endif sif (!cpuis("STM32F4*")) group.long 0xB68++0x03 line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else if ((per.l(ad:0x50000000+0xB68-0x08)&0xC0000)==0x00) group.long 0xB68++0x03 line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB68++0x03 line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif endif endif group.long 0x910++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ0,OTG_FS Device IN Endpoint 0 Transfer Size Register" bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0xB10++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" ",1,2,3" bitfld.long 0x00 19. " PKTCNT ,Packet count" "0,1" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x930++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ1,OTG_FS Device IN Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x950++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ2,OTG_FS Device IN Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x970++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ3,OTG_FS Device IN Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x990++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ4,OTG_FS Device IN Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9B0++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ5,OTG_FS Device IN Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0x930++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x950++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x970++0x03 line.long 0x00 "OTG_FS_DIEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rgroup.long 0x918++0x03 line.long 0x00 "OTG_FS_DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x938++0x03 line.long 0x00 "OTG_FS_DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x958++0x03 line.long 0x00 "OTG_FS_DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x978++0x03 line.long 0x00 "OTG_FS_DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x998++0x03 line.long 0x00 "OTG_FS_DTXFSTS4,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9B8++0x03 line.long 0x00 "OTG_FS_DTXFSTS5,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" else rgroup.long 0x918++0x03 line.long 0x00 "OTG_FS_DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x938++0x03 line.long 0x00 "OTG_FS_DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x958++0x03 line.long 0x00 "OTG_FS_DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x978++0x03 line.long 0x00 "OTG_FS_DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" endif sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") group.long 0xB10++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" bitfld.long 0x00 19. " PKTCNT ,Packet count" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..." else bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..." else bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..." else bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x40000) group.long 0xB90++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..." else bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x00000) group.long 0xB90++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB90++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x40000) group.long 0xBB0++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register" sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..." else bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" endif hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x00000) group.long 0xBB0++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBB0++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif else sif (cpuis("STM32F4*")) if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif else if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif endif sif (cpuis("STM32F4*")) if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif else if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif endif sif (cpuis("STM32F4*")) if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif else if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif endif endif tree.end width 16. tree "Power and clock gating control and status registers" group.long 0xE00++0x03 line.long 0x00 "OTG_FS_PCGCCTL,OTG_FS Power And Clock Gating Control Register" sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 7. " SUSP ,Deep Sleep" "Disabled,Enabled" rbitfld.long 0x00 6. " PHYSLEEP ,PHY in Sleep" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ENL1GTG ,Enable Sleep clock gating" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended" else bitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended" endif bitfld.long 0x00 1. " GATEHCLK ,Gate HCLK" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " STPPCLK ,Stop PHY clock" "Not stopped,Stopped" tree.end width 0x0B tree.end sif (!cpuis("STM32F401*")&&(!cpuis("STM32F411*"))&&(!cpuis("STM32F410*"))&&(!cpuis("STM32F412*"))&&(!cpuis("STM32F413*"))&&(!cpuis("STM32F423?H"))) tree "USB_OTG_HS (USB On-the-go High-speed)" base ad:0x40040000 width 17. tree "OTG_HS Global Registers" if (((per.l((ad:0x40040000+0x14)))&0x1)==0x1) group.long 0x00++0x1B line.long 0x00 "OTG_HS_GOTGCTL,OTG_HS Control And Status Register" sif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 20. " OTGVER ,OTG version" "1.3,2.0" textline " " endif rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Not valid,Valid" rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short" textline " " rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled" endif textline " " bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "0,1" bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "0,1" bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled" endif line.long 0x04 "OTG_HS_GOTGINT,OTG_HS Interrupt Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed" textline " " endif eventfld.long 0x04 19. " DBCDNE ,Debounce done" "Not done,Done" eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed" textline " " eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected" eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed" textline " " eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed" eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected" line.long 0x08 "OTG_HS_GAHBCFG,OTG_HS AHB Configuration Register" bitfld.long 0x08 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty" endif textline " " bitfld.long 0x08 5. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1.--4. " HBSTLEN ,Burst length/type" "Single,INCR,,INCR4,,INCR8,,INCR16,?..." bitfld.long 0x08 0. " GINT ,Global interrupt mask" "Masked,Unmasked" line.long 0x0C "OTG_HS_GUSBCFG,OTG_HS USB Configuration Register" sif !cpuis("STM32F446*") bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High" textline " " endif bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced" textline " " bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced" bitfld.long 0x0C 25. " ULPIIPD ,ULPI interface protect disable" "No,Yes" textline " " bitfld.long 0x0C 24. " PTCI ,Indicator pass through" "Not qualified,Qualified" bitfld.long 0x0C 23. " PCCI ,Indicator complement" "Not inverted,Inverted" textline " " bitfld.long 0x0C 22. " TSDPS ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel" bitfld.long 0x0C 21. " ULPIEVBUSI ,ULPI external VBUS indicator" "Internal,External" textline " " bitfld.long 0x0C 20. " ULPIEVBUSD ,ULPI External VBUS Drive" "Internal,External" bitfld.long 0x0C 19. " ULPICSM ,ULPI Clock SuspendM" "Power down,Power up" textline " " bitfld.long 0x0C 18. " ULPIAR ,ULPI Auto-resume enable" "Disabled,Enabled" bitfld.long 0x0C 17. " ULPIFSLS ,ULPI FS/LS select" "ULPI,ULPI FS/LS" textline " " bitfld.long 0x0C 15. " PHYLPCS ,PHY Low-power clock select" "480 MHz,48 MHz" bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x0C 6. " PHSEL ,USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select" "USB 2.0 HS,USB 1.1 FS" textline " " endif sif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x0C 4. " ULPI_SEL ,High speed interface select" "UTMI,ULPI" textline " " endif bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS Reset Register" rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Busy,Idle" rbitfld.long 0x10 30. " DMAREQ ,DMA request signal" "Not requested,Requested" textline " " bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic,Periodic,,,,,,,,,,,,,,,All,?..." bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit" textline " " bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High" bitfld.long 0x10 2. " FCRST ,Host frame counter reset" "No reset,Reset" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset" textline " " else bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset" textline " " endif bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS Core Interrupt Register" rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Peripheral mode,Host mode" eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" sif cpuis("STM32F469*")||cpuis("STM32F479*") textline " " eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "No interrupt,Interrupt" endif rbitfld.long 0x14 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x14 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt" rbitfld.long 0x14 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 22. " DATAFSUSP ,Data fetch suspended (DMA mode)" "No interrupt,Interrupt" eventfld.long 0x14 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt" textline " " sif (cpuis("STM32F4*")) rbitfld.long 0x14 5. " NPTXFE ,Non-periodic TxFIFO empty" "No interrupt,Interrupt" textline " " endif rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty" eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started" textline " " rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS Interrupt Mask Register" sif cpuis("STM32F469")||cpuis("STM32F479") bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" textline " " endif bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x18 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked" textline " " endif bitfld.long 0x18 26. " PTXFEM ,Periodic TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x18 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked" textline " " rbitfld.long 0x18 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked" bitfld.long 0x18 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked" textline " " bitfld.long 0x18 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" textline " " bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked" bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" rgroup.long 0x1C++0x03 line.long 0x00 "OTG_HS_GRXSTSR,OTG_HS Receive Status Debug Read Register" bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..." bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA" textline " " hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x20++0x03 hide.long 0x00 "OTG_HS_GRXSTSP,OTG Status Read And Pop Register" in else group.long 0x00++0x1B line.long 0x00 "OTG_HS_GOTGCTL,OTG_HS Control And Status Register" sif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 20. " OTGVER ,OTG version" "1.3,2.0" textline " " endif rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Not valid,Valid" rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled" bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested" textline " " rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Successful" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "0,1" bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " SRQ ,Session request" "Not requested,Requested" textline " " rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Successful" line.long 0x04 "OTG_HS_GOTGINT,OTG_HS Interrupt Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed" textline " " endif eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed" eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected" textline " " eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed" eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed" textline " " eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected" line.long 0x08 "OTG_HS_GAHBCFG,OTG_HS AHB Configuration Register" sif (!cpuis("STM32F4*")) bitfld.long 0x08 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty" else bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty" endif textline " " bitfld.long 0x08 5. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1.--4. " HBSTLEN ,Burst length/type" "Single,INCR,,INCR4,,INCR8,,INCR16,?..." bitfld.long 0x08 0. " GINT ,Global interrupt mask" "Masked,Unmasked" line.long 0x0C "OTG_HS_GUSBCFG,OTG_HS USB Configuration Register" sif !cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High" textline " " endif bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced" textline " " bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced" bitfld.long 0x0C 25. " ULPIIPD ,ULPI interface protect disable" "No,Yes" textline " " bitfld.long 0x0C 24. " PTCI ,Indicator pass through" "Not qualified,Qualified" bitfld.long 0x0C 23. " PCCI ,Indicator complement" "Not inverted,Inverted" textline " " bitfld.long 0x0C 22. " TSDPS ,TermSel DLine pulsing selection" "Utmi_txvalid,Utmi_termsel" bitfld.long 0x0C 21. " ULPIEVBUSI ,ULPI external VBUS indicator" "Internal,External" textline " " bitfld.long 0x0C 20. " ULPIEVBUSD ,ULPI External VBUS Drive" "Internal,External" bitfld.long 0x0C 19. " ULPICSM ,ULPI Clock SuspendM" "Power down,Power up" textline " " bitfld.long 0x0C 18. " ULPIAR ,ULPI Auto-resume enable" "Disabled,Enabled" bitfld.long 0x0C 17. " ULPIFSLS ,ULPI FS/LS select" "ULPI,ULPI FS/LS" textline " " bitfld.long 0x0C 15. " PHYLPCS ,PHY Low-power clock select" "480 MHz,48 MHz" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" ",,,,,16-bit,,,,8-bit,?..." else textline " " bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline " " bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled" sif (!cpuis("STM32F4*")) textline " " bitfld.long 0x0C 7. " PHYSEL ,Full Speed serial transceiver select" "0,1" endif textline " " bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled" textline " " sif (cpuis("STM32F4*")) bitfld.long 0x0C 6. " PHSEL ,USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select" "USB 2.0 HS,USB 1.1 FS" textline " " endif sif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x0C 4. " ULPI_SEL ,High speed interface select" "UTMI,ULPI" textline " " endif bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS Reset Register" rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Busy,Idle" rbitfld.long 0x10 30. " DMAREQ ,DMA request signal" "Not requested,Requested" textline " " bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,All,?..." bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit" textline " " bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset" else bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset" endif textline " " bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS Core Interrupt Register" rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Peripheral mode,Host mode" eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt" eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed" textline " " sif cpuis("STM32F469*")||cpuis("STM32F479*") eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x14 22. " DATAFSUSP ,Data fetch suspended (DMA mode)" "No interrupt,Interrupt" eventfld.long 0x14 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No interrupt,Interrupt" textline " " eventfld.long 0x14 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt" rbitfld.long 0x14 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt" eventfld.long 0x14 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt" eventfld.long 0x14 13. " ENUMDNE ,Enumeration done" "Not done,Done" textline " " eventfld.long 0x14 12. " USBRST ,USB reset" "No reset,Reset" eventfld.long 0x14 11. " USBSUSP ,USB suspend" "Not suspended,Suspended" textline " " eventfld.long 0x14 10. " ESUSP ,Early suspend" "Not suspended,Suspended" rbitfld.long 0x14 7. " GONAKEFF ,Global OUT NAK effective" "Low,High" textline " " rbitfld.long 0x14 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High" rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty" textline " " eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started" rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS Interrupt Mask Register" bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked" bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " bitfld.long 0x18 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked" endif textline " " bitfld.long 0x18 22. " FSUSPM ,Data fetch suspended mask" "Masked,Unmasked" bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked" textline " " bitfld.long 0x18 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked" bitfld.long 0x18 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked" sif !cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") textline " " bitfld.long 0x18 17. " EPMISM ,Endpoint mismatch interrupt mask" "Masked,Unmasked" endif textline " " bitfld.long 0x18 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked" bitfld.long 0x18 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x18 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked" bitfld.long 0x18 12. " USBRST ,USB reset mask" "Masked,Unmasked" textline " " bitfld.long 0x18 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked" bitfld.long 0x18 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked" textline " " bitfld.long 0x18 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked" bitfld.long 0x18 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked" textline " " bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked" bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked" textline " " bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked" bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked" rgroup.long 0x1C++0x03 line.long 0x00 "OTG_HS_GRXSTSR,OTG_HS Receive Status Debug Read Register" bitfld.long 0x00 21.--24. " FRMNUM ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,Transaction completed,,SETUP data packet received,?..." textline " " bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA" hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count" textline " " bitfld.long 0x00 0.--3. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x20++0x03 hide.long 0x00 "OTG_HS_GRXSTSP,OTG Status Read And Pop Register" in endif group.long 0x24++0x03 line.long 0x00 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO Size Register" hexmask.long.word 0x00 0.--15. 1. " RXFD ,RxFIFO depth" if (((per.l((ad:0x40040000+0x14)))&0x1)==0x1) group.long 0x28++0x03 sif cpuis("STM32F469*")||cpuis("STM32F479*") line.long 0x00 "OTG_HNPTXFSIZ,OTG_HS Host Non-periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSA ,Non-periodic transmit RAM start address" else line.long 0x00 "OTG_HS_GNPTXFSIZ,OTG_HS Non-periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSA ,Non-periodic transmit RAM start address" endif rgroup.long 0x2C++0x03 sif cpuis("STM32F469*")||cpuis("STM32F479*") line.long 0x00 "OTG_HNPTXSTS,OTG Non-periodic Transmit FIFO/Queue Status Register" bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue [CH/EP number]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,Channel halt,Channel halt" textline " " bitfld.long 0x00 24. " NPTXQTOP[24] ,Top of the nonperiodic transmit request queue" "Not terminated,Terminated" textline " " hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available" else line.long 0x00 "OTG_HS_GNPTXSTS,OTG_HS Non-periodic Transmit FIFO/Queue Status Register" bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue [CH/EP number]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif (!cpuis("STM32F4*")) bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,,Channel halt" else bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,PING/CSPLIT,Channel halt" endif textline " " bitfld.long 0x00 24. " NPTXQTOP[24] ,Top of the nonperiodic transmit request queue" "Not terminated,Terminated" textline " " hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available" textline " " hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available" endif else group.long 0x28++0x03 sif (!cpuis("STM32F4*")) line.long 0x00 "OTG_HS_GNPTXFSIZ,OTG_HS Non-periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " T0XFD ,Non-periodic TxFIFO depth" textline " " hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Non-periodic transmit RAM start address" elif cpuis("STM32F469*")||cpuis("STM32F479*") line.long 0x00 "OTG_HS_DIEPTXF0,Endpoint 0 Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " T0XFD ,Endpoint 0 TxFIFO depth" textline " " hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Endpoint 0 transmit RAM start address" else line.long 0x00 "OTG_HS_TX0FSIZ,Endpoint 0 Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " T0XFD ,Endpoint 0 TxFIFO depth" textline " " hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Endpoint 0 transmit RAM start address" endif hgroup.long 0x2C++0x03 sif cpuis("STM32F469*")||cpuis("STM32F479*") hide.long 0x00 "OTG_HS_HNPTXSTS,OTG Non-periodic Transmit FIFO/Queue Status Register" else hide.long 0x00 "OTG_HS_GNPTXSTS,OTG_HS Non-periodic Transmit FIFO/Queue Status Register" endif endif group.long 0x30++0x3 line.long 0x00 "OTG_HS_GI2CCTL,OTG_HS I2C Access Register" bitfld.long 0x00 31. " BSYDNE ,I2C Busy/Done" "Done,Busy" bitfld.long 0x00 30. " RW ,Read/Write Indicator" "Write,Read" textline " " bitfld.long 0x00 28. " I2CDATSE0 ,I2C DatSe0 USB mode" "VP_VM USB,DAT_SE0 USB" bitfld.long 0x00 26.--27. " I2CDEVADR ,I2C Device Address" "0,1,2,3" textline " " bitfld.long 0x00 24. " ACK ,I2C ACK" "NAK,ACK" bitfld.long 0x00 23. " I2CEN ,I2C Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 16.--22. 1. " ADDR ,I2C Address" hexmask.long.byte 0x00 8.--15. 1. " REGADDR ,I2C Register Address" textline " " hexmask.long.byte 0x00 0.--7. 1. " RWDATA ,I2C Read/Write Data" group.long 0x38++0x07 line.long 0x00 "OTG_HS_GCCFG,OTG_HS General Core Configuration Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled" textline " " else bitfld.long 0x00 21. " NOVBUSSENS ,VBUS sensing disable" "No,Yes" bitfld.long 0x00 20. " SOFOUTEN ,SOF output enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " VBUSBSEN ,Enable the VBUS sensing B device" "Disabled,Enabled" bitfld.long 0x00 18. " VBUSASEN ,Enable the VBUS sensing A device" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " I2CPADEN ,I2C bus for the external I2C PHY interface" "Disabled,Enabled" endif sif (cpuis("STM32F4*")) textline " " bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down" else textline " " bitfld.long 0x00 16. " PWRDWN ,Power down" "Not active,Active" endif line.long 0x04 "OTG_HS_CID,OTG_HS Core ID Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l((ad:0x40040000+0x14)))&0x1)==0x1) group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Sending,Cleared" bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM Channel Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes" textline " " rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1" rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..." textline " " bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled" bitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1" textline " " bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000" bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register" bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled" rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes" textline " " rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1" rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK" textline " " bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..." textline " " bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled" rbitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1" textline " " rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000" bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled" endif endif group.long 0x100++0x03 line.long 0x00 "OTG_HS_HPTXFSIZ,OTG_HS Host Periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " PTXFD ,Host periodic TxFIFO depth" hexmask.long.word 0x00 0.--15. 1. " PTXSA ,Host periodic TxFIFO start address" sif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x104++0x03 line.long 0x00 "OTG_HS_DIEPTXF1,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 1 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 1 transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_HS_DIEPTXF2,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 2 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 2 transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_HS_DIEPTXF3,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 3 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 3 transmit RAM start address" group.long 0x110++0x03 line.long 0x00 "OTG_HS_DIEPTXF4,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 4 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 4 transmit RAM start address" group.long 0x114++0x03 line.long 0x00 "OTG_HS_DIEPTXF5,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 5 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 5 transmit RAM start address" group.long 0x118++0x03 line.long 0x00 "OTG_HS_DIEPTXF6,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 6 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 6 transmit RAM start address" group.long 0x11C++0x03 line.long 0x00 "OTG_HS_DIEPTXF7,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 7 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 7 transmit RAM start address" group.long 0x120++0x03 line.long 0x00 "OTG_HS_DIEPTXF8,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 8 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 8 transmit RAM start address" else group.long 0x104++0x03 line.long 0x00 "OTG_HS_DIEPTXF1,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 1 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 1 transmit RAM start address" group.long 0x108++0x03 line.long 0x00 "OTG_HS_DIEPTXF2,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 2 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 2 transmit RAM start address" group.long 0x10C++0x03 line.long 0x00 "OTG_HS_DIEPTXF3,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 3 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 3 transmit RAM start address" group.long 0x110++0x03 line.long 0x00 "OTG_HS_DIEPTXF4,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 4 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 4 transmit RAM start address" group.long 0x114++0x03 line.long 0x00 "OTG_HS_DIEPTXF5,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 5 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 5 transmit RAM start address" group.long 0x118++0x03 line.long 0x00 "OTG_HS_DIEPTXF6,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 6 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 6 transmit RAM start address" group.long 0x11C++0x03 line.long 0x00 "OTG_HS_DIEPTXF7,OTG_HS Device IN Endpoint Transmit FIFO Size Register" hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO 7 depth" hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint TxFIFO 7 transmit RAM start address" endif tree.end width 18. tree "Host mode registers" if (((per.l((ad:0x40040000+0x14)))&0x1)==0x1) group.long 0x400++0x07 line.long 0x00 "OTG_HS_HCFG,OTG_HS Host Configuration Register" rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported" bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,-/6 MHz,?..." line.long 0x04 "OTG_HS_HFIR,OTG_HS Host Frame Interval Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 16. " RLDCTRL ,Reload control" "Cannot reload,Can Reload" textline " " endif hexmask.long.word 0x04 0.--15. 1. " FRIVL ,Frame interval" rgroup.long 0x408++0x03 line.long 0x00 "OTG_HS_HFNUM,OTG_HS Host Frame Number/Frame Time Remaining Register" hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining" hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number" group.long 0x410++0x03 line.long 0x00 "OTG_HS_HPTXSTS,OTG_HS_Host Periodic Transmit FIFO/Queue Status Register" sif (!cpuis("STM32F4*")) hexmask.long.byte 0x00 24.--31. 1. " PTXQTOP ,Top of the periodic transmit request queue" textline " " else bitfld.long 0x00 31. " PTXQTOP[31] , Odd/Even rame" "Even,Odd" bitfld.long 0x00 27.--30. " PTXQTOP[27:30] ,Channel/endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 25.--26. " PTXQTOP[25:26] ,Type" "IN/OUT,Zero-lenght,,Disable" bitfld.long 0x00 24. " PTXQTOP[24] ,Terminate" "No terminate,Terminate" textline " " endif hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available" hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available" rgroup.long 0x414++0x03 line.long 0x00 "OTG_HS_HAINT,OTG_HS Host All Channels Interrupt Register" bitfld.long 0x00 15. " HAINT[15] ,Channel 15 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " HAINT[14] ,Channel 14 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " HAINT[13] ,Channel 13 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " HAINT[12] ,Channel 12 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " HAINT[11] ,Channel 11 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " HAINT[10] ,Channel 10 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " HAINT[9] ,Channel 9 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " HAINT[8] ,Channel 8 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " HAINT[7] ,Channel 7 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " HAINT[6] ,Channel 6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " HAINT[5] ,Channel 5 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 4. " HAINT[4] ,Channel 4 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " HAINT[3] ,Channel 3 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " HAINT[2] ,Channel 2 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " HAINT[1] ,Channel 1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " HAINT[0] ,Channel 0 interrupt" "No interrupt,Interrupt" group.long 0x418++0x03 line.long 0x00 "OTG_HS_HAINTMSK,OTG_HS Host All Channels Interrupt Mask Register" bitfld.long 0x00 15. " HAINTM[15] ,Channel interrupt mask 15" "Masked,Unmasked" bitfld.long 0x00 14. " HAINTM[14] ,Channel interrupt mask 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " HAINTM[13] ,Channel interrupt mask 13" "Masked,Unmasked" bitfld.long 0x00 12. " HAINTM[12] ,Channel interrupt mask 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " HAINTM[11] ,Channel interrupt mask 11" "Masked,Unmasked" bitfld.long 0x00 10. " HAINTM[10] ,Channel interrupt mask 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " HAINTM[9] ,Channel interrupt mask 9" "Masked,Unmasked" bitfld.long 0x00 8. " HAINTM[8] ,Channel interrupt mask 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " HAINTM[7] ,Channel interrupt mask 7" "Masked,Unmasked" bitfld.long 0x00 6. " HAINTM[6] ,Channel interrupt mask 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " HAINTM[5] ,Channel interrupt mask 5" "Masked,Unmasked" bitfld.long 0x00 4. " HAINTM[4] ,Channel interrupt mask 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " HAINTM[3] ,Channel interrupt mask 3" "Masked,Unmasked" bitfld.long 0x00 2. " HAINTM[2] ,Channel interrupt mask 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " HAINTM[1] ,Channel interrupt mask 1" "Masked,Unmasked" bitfld.long 0x00 0. " HAINTM[0] ,Channel interrupt mask 0" "Masked,Unmasked" group.long 0x440++0x03 line.long 0x00 "OTG_HS_HPRT,OTG_HS Host Port Control And Status Register" rbitfld.long 0x00 17.--18. " PSPD ,Port speed" "High,Full,Low,?..." bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..." textline " " bitfld.long 0x00 12. " PPWR ,Port power" "Off,On" rbitfld.long 0x00 11. " PLSTS[1] ,Port line status (Logic level of OTG_HS_HS_DP)" "Low,High" textline " " rbitfld.long 0x00 10. " PLSTS[0] ,Port line status (Logic level of OTG_HS_HS_DM)" "Low,High" bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed" textline " " eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed" rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active" textline " " eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected" rbitfld.long 0x00 0. " PCSTS ,Port connect status" "No device,Device" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x500++0x17 line.long 0x00 "OTG_HS_HCCHAR0,OTG_HS Host Channel-0 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT0,OTG_HS Host Channel-0 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT0,OTG_FH Host Channel-0 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK0,OTG_HS Host Channel-0 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ0,OTG_HS Host Channel-0 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA0,OTG_HS Host Channel-0 DMA Address Register" group.long 0x520++0x17 line.long 0x00 "OTG_HS_HCCHAR1,OTG_HS Host Channel-1 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT1,OTG_HS Host Channel-1 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT1,OTG_FH Host Channel-1 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK1,OTG_HS Host Channel-1 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ1,OTG_HS Host Channel-1 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA1,OTG_HS Host Channel-1 DMA Address Register" group.long 0x540++0x17 line.long 0x00 "OTG_HS_HCCHAR2,OTG_HS Host Channel-2 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT2,OTG_HS Host Channel-2 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT2,OTG_FH Host Channel-2 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK2,OTG_HS Host Channel-2 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ2,OTG_HS Host Channel-2 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA2,OTG_HS Host Channel-2 DMA Address Register" group.long 0x560++0x17 line.long 0x00 "OTG_HS_HCCHAR3,OTG_HS Host Channel-3 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT3,OTG_HS Host Channel-3 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT3,OTG_FH Host Channel-3 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK3,OTG_HS Host Channel-3 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ3,OTG_HS Host Channel-3 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA3,OTG_HS Host Channel-3 DMA Address Register" group.long 0x580++0x17 line.long 0x00 "OTG_HS_HCCHAR4,OTG_HS Host Channel-4 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT4,OTG_HS Host Channel-4 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT4,OTG_FH Host Channel-4 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK4,OTG_HS Host Channel-4 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ4,OTG_HS Host Channel-4 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA4,OTG_HS Host Channel-4 DMA Address Register" group.long 0x5A0++0x17 line.long 0x00 "OTG_HS_HCCHAR5,OTG_HS Host Channel-5 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT5,OTG_HS Host Channel-5 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT5,OTG_FH Host Channel-5 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK5,OTG_HS Host Channel-5 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ5,OTG_HS Host Channel-5 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA5,OTG_HS Host Channel-5 DMA Address Register" group.long 0x5C0++0x17 line.long 0x00 "OTG_HS_HCCHAR6,OTG_HS Host Channel-6 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT6,OTG_HS Host Channel-6 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT6,OTG_FH Host Channel-6 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK6,OTG_HS Host Channel-6 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ6,OTG_HS Host Channel-6 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA6,OTG_HS Host Channel-6 DMA Address Register" group.long 0x5E0++0x17 line.long 0x00 "OTG_HS_HCCHAR7,OTG_HS Host Channel-7 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT7,OTG_HS Host Channel-7 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT7,OTG_FH Host Channel-7 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK7,OTG_HS Host Channel-7 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ7,OTG_HS Host Channel-7 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA7,OTG_HS Host Channel-7 DMA Address Register" group.long 0x600++0x17 line.long 0x00 "OTG_HS_HCCHAR8,OTG_HS Host Channel-8 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT8,OTG_HS Host Channel-8 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT8,OTG_FH Host Channel-8 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK8,OTG_HS Host Channel-8 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ8,OTG_HS Host Channel-8 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA8,OTG_HS Host Channel-8 DMA Address Register" group.long 0x620++0x17 line.long 0x00 "OTG_HS_HCCHAR9,OTG_HS Host Channel-9 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT9,OTG_HS Host Channel-9 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT9,OTG_FH Host Channel-9 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK9,OTG_HS Host Channel-9 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ9,OTG_HS Host Channel-9 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA9,OTG_HS Host Channel-9 DMA Address Register" group.long 0x640++0x17 line.long 0x00 "OTG_HS_HCCHAR10,OTG_HS Host Channel-10 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT10,OTG_HS Host Channel-10 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT10,OTG_FH Host Channel-10 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK10,OTG_HS Host Channel-10 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ10,OTG_HS Host Channel-10 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA10,OTG_HS Host Channel-10 DMA Address Register" group.long 0x660++0x17 line.long 0x00 "OTG_HS_HCCHAR11,OTG_HS Host Channel-11 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT11,OTG_HS Host Channel-11 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT11,OTG_FH Host Channel-11 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK11,OTG_HS Host Channel-11 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ11,OTG_HS Host Channel-11 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA11,OTG_HS Host Channel-11 DMA Address Register" group.long 0x680++0x17 line.long 0x00 "OTG_HS_HCCHAR12,OTG_HS Host Channel-12 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT12,OTG_HS Host Channel-12 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT12,OTG_FH Host Channel-12 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK12,OTG_HS Host Channel-12 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ12,OTG_HS Host Channel-12 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA12,OTG_HS Host Channel-12 DMA Address Register" group.long 0x6A0++0x17 line.long 0x00 "OTG_HS_HCCHAR13,OTG_HS Host Channel-13 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT13,OTG_HS Host Channel-13 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT13,OTG_FH Host Channel-13 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK13,OTG_HS Host Channel-13 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ13,OTG_HS Host Channel-13 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA13,OTG_HS Host Channel-13 DMA Address Register" group.long 0x6C0++0x17 line.long 0x00 "OTG_HS_HCCHAR14,OTG_HS Host Channel-14 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT14,OTG_HS Host Channel-14 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT14,OTG_FH Host Channel-14 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK14,OTG_HS Host Channel-14 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ14,OTG_HS Host Channel-14 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA14,OTG_HS Host Channel-14 DMA Address Register" group.long 0x6E0++0x17 line.long 0x00 "OTG_HS_HCCHAR15,OTG_HS Host Channel-15 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT15,OTG_HS Host Channel-15 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT15,OTG_FH Host Channel-15 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK15,OTG_HS Host Channel-15 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ15,OTG_HS Host Channel-15 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA15,OTG_HS Host Channel-15 DMA Address Register" else group.long 0x500++0x17 line.long 0x00 "OTG_HS_HCCHAR0,OTG_HS Host Channel-0 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT0,OTG_HS Host Channel-0 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT0,OTG_FH Host Channel-0 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK0,OTG_HS Host Channel-0 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ0,OTG_HS Host Channel-0 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA0,OTG_HS Host Channel-0 DMA Address Register" group.long 0x520++0x17 line.long 0x00 "OTG_HS_HCCHAR1,OTG_HS Host Channel-1 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT1,OTG_HS Host Channel-1 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT1,OTG_FH Host Channel-1 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK1,OTG_HS Host Channel-1 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ1,OTG_HS Host Channel-1 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA1,OTG_HS Host Channel-1 DMA Address Register" group.long 0x540++0x17 line.long 0x00 "OTG_HS_HCCHAR2,OTG_HS Host Channel-2 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT2,OTG_HS Host Channel-2 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT2,OTG_FH Host Channel-2 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK2,OTG_HS Host Channel-2 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ2,OTG_HS Host Channel-2 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA2,OTG_HS Host Channel-2 DMA Address Register" group.long 0x560++0x17 line.long 0x00 "OTG_HS_HCCHAR3,OTG_HS Host Channel-3 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT3,OTG_HS Host Channel-3 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT3,OTG_FH Host Channel-3 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK3,OTG_HS Host Channel-3 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ3,OTG_HS Host Channel-3 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA3,OTG_HS Host Channel-3 DMA Address Register" group.long 0x580++0x17 line.long 0x00 "OTG_HS_HCCHAR4,OTG_HS Host Channel-4 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT4,OTG_HS Host Channel-4 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT4,OTG_FH Host Channel-4 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK4,OTG_HS Host Channel-4 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ4,OTG_HS Host Channel-4 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA4,OTG_HS Host Channel-4 DMA Address Register" group.long 0x5A0++0x17 line.long 0x00 "OTG_HS_HCCHAR5,OTG_HS Host Channel-5 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT5,OTG_HS Host Channel-5 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT5,OTG_FH Host Channel-5 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK5,OTG_HS Host Channel-5 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ5,OTG_HS Host Channel-5 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA5,OTG_HS Host Channel-5 DMA Address Register" group.long 0x5C0++0x17 line.long 0x00 "OTG_HS_HCCHAR6,OTG_HS Host Channel-6 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT6,OTG_HS Host Channel-6 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT6,OTG_FH Host Channel-6 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK6,OTG_HS Host Channel-6 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ6,OTG_HS Host Channel-6 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA6,OTG_HS Host Channel-6 DMA Address Register" group.long 0x5E0++0x17 line.long 0x00 "OTG_HS_HCCHAR7,OTG_HS Host Channel-7 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT7,OTG_HS Host Channel-7 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT7,OTG_FH Host Channel-7 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK7,OTG_HS Host Channel-7 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ7,OTG_HS Host Channel-7 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA7,OTG_HS Host Channel-7 DMA Address Register" group.long 0x600++0x17 line.long 0x00 "OTG_HS_HCCHAR8,OTG_HS Host Channel-8 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT8,OTG_HS Host Channel-8 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT8,OTG_FH Host Channel-8 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK8,OTG_HS Host Channel-8 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ8,OTG_HS Host Channel-8 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA8,OTG_HS Host Channel-8 DMA Address Register" group.long 0x620++0x17 line.long 0x00 "OTG_HS_HCCHAR9,OTG_HS Host Channel-9 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT9,OTG_HS Host Channel-9 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT9,OTG_FH Host Channel-9 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK9,OTG_HS Host Channel-9 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ9,OTG_HS Host Channel-9 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA9,OTG_HS Host Channel-9 DMA Address Register" group.long 0x640++0x17 line.long 0x00 "OTG_HS_HCCHAR10,OTG_HS Host Channel-10 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT10,OTG_HS Host Channel-10 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT10,OTG_FH Host Channel-10 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK10,OTG_HS Host Channel-10 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ10,OTG_HS Host Channel-10 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA10,OTG_HS Host Channel-10 DMA Address Register" group.long 0x660++0x17 line.long 0x00 "OTG_HS_HCCHAR11,OTG_HS Host Channel-11 Characteristics Register" bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled" bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes" textline " " bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd" hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address" textline " " bitfld.long 0x00 20.--21. " MC ,Multi Count (MC)/Error Count (EC)" ",1,2,3" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No,Yes" bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN" textline " " bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" line.long 0x04 "OTG_HS_HCSPLT11,OTG_HS Host Channel-11 Split Control Register" bitfld.long 0x04 31. " SPLITEN ,Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " COMPLSPLT ,Do complete split" "Not requested,Requested" textline " " bitfld.long 0x04 14.--15. " XACTPOS ,Transaction position" "Middle,Last,First,All" textline " " hexmask.long.word 0x04 7.--13. 0x80 " HUBADDR ,Hub address" textline " " hexmask.long.byte 0x04 0.--6. 1. " PRTADDR ,Port address" line.long 0x08 "OTG_HS_HCINT11,OTG_FH Host Channel-11 Interrupt Register" eventfld.long 0x08 10. " DTERR ,Data toggle error" "No error,Error" eventfld.long 0x08 9. " FRMOR ,Frame overrun" "No overrun,Overrun" textline " " eventfld.long 0x08 8. " BBERR ,Babble error" "No error,Error" eventfld.long 0x08 7. " TXERR ,Transaction error" "No error,Error" textline " " eventfld.long 0x08 6. " NYET ,Response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt" sif (cpuis("STM32F4*")) eventfld.long 0x08 2. " AHBERR ,AHB error" "No error,Error" textline " " endif eventfld.long 0x08 1. " CHH ,Channel halted" "Not halted,Halted" textline " " eventfld.long 0x08 0. " XFRC ,Transfer completed" "Not completed,Completed" line.long 0x0C "OTG_HS_HCINTMSK11,OTG_HS Host Channel-11 Interrupt Mask Register" bitfld.long 0x0C 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked" bitfld.long 0x0C 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 8. " BBERRM ,Babble error mask" "Masked,Unmasked" bitfld.long 0x0C 7. " TXERRM ,Transaction error mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 6. " NYET ,Response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked" bitfld.long 0x0C 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 2. " AHBERR ,AHB error" "Masked,Unmasked" bitfld.long 0x0C 1. " CHHM ,Channel halted mask" "Masked,Unmasked" textline " " bitfld.long 0x0C 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked" line.long 0x10 "OTG_HS_HCTSIZ11,OTG_HS Host Channel-11 Transfer Size Register" sif !cpuis("STM32F446*") bitfld.long 0x10 31. " DOPING ,Do ping" "No ping,Ping" textline " " endif bitfld.long 0x10 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA" textline " " hexmask.long.word 0x10 19.--28. 1. " PKTCNT ,Packet count" textline " " hexmask.long.tbyte 0x10 0.--18. 1. " XFRSIZ ,Transfer size" line.long 0x14 "OTG_HS_HCDMA11,OTG_HS Host Channel-11 DMA Address Register" endif else hgroup.long 0x400++0x03 hide.long 0x00 "OTG_HS_HCFG,OTG_HS Host Configuration Register" hgroup.long 0x404++0x03 hide.long 0x00 "OTG_HS_HFIR,OTG_HS Host Frame Interval Register" hgroup.long 0x408++0x03 hide.long 0x00 "OTG_HS_HFNUM,OTG_HS Host Frame Number/Frame Time Remaining Register" hgroup.long 0x410++0x03 hide.long 0x00 "OTG_HS_HPTXSTS,OTG_HS_Host Periodic Transmit FIFO/Queue Status Register" hgroup.long 0x414++0x03 hide.long 0x00 "OTG_HS_HAINT,OTG_HS Host All Channels Interrupt Register" hgroup.long 0x418++0x03 hide.long 0x00 "OTG_HS_HAINTMSK,OTG_HS Host All Channels Interrupt Mask Register" hgroup.long 0x440++0x03 hide.long 0x00 "OTG_HS_HPRT,OTG_HS Host Port Control And Status Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") hgroup.long 0x500++0x03 hide.long 0x00 "OTG_HS_HCCHAR0,OTG_HS Host Channel-0 Characteristics Register" hgroup.long (0x500+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT0,OTG_HS Host Channel-0 Split Control Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT0,OTG_HS Host Channel-0 Interrupt Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK0,OTG_HS Host Channel-0 Interrupt Mask Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ0,OTG_HS Host Channel-0 Transfer Size Register" hgroup.long (0x500+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA0,OTG_HS Host Channel-0 DMA Address Register" hgroup.long 0x520++0x03 hide.long 0x00 "OTG_HS_HCCHAR1,OTG_HS Host Channel-1 Characteristics Register" hgroup.long (0x520+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT1,OTG_HS Host Channel-1 Split Control Register" hgroup.long (0x520+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT1,OTG_HS Host Channel-1 Interrupt Register" hgroup.long (0x520+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK1,OTG_HS Host Channel-1 Interrupt Mask Register" hgroup.long (0x520+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ1,OTG_HS Host Channel-1 Transfer Size Register" hgroup.long (0x520+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA1,OTG_HS Host Channel-1 DMA Address Register" hgroup.long 0x540++0x03 hide.long 0x00 "OTG_HS_HCCHAR2,OTG_HS Host Channel-2 Characteristics Register" hgroup.long (0x540+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT2,OTG_HS Host Channel-2 Split Control Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT2,OTG_HS Host Channel-2 Interrupt Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK2,OTG_HS Host Channel-2 Interrupt Mask Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ2,OTG_HS Host Channel-2 Transfer Size Register" hgroup.long (0x540+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA2,OTG_HS Host Channel-2 DMA Address Register" hgroup.long 0x560++0x03 hide.long 0x00 "OTG_HS_HCCHAR3,OTG_HS Host Channel-3 Characteristics Register" hgroup.long (0x560+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT3,OTG_HS Host Channel-3 Split Control Register" hgroup.long (0x560+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT3,OTG_HS Host Channel-3 Interrupt Register" hgroup.long (0x560+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK3,OTG_HS Host Channel-3 Interrupt Mask Register" hgroup.long (0x560+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ3,OTG_HS Host Channel-3 Transfer Size Register" hgroup.long (0x560+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA3,OTG_HS Host Channel-3 DMA Address Register" hgroup.long 0x580++0x03 hide.long 0x00 "OTG_HS_HCCHAR4,OTG_HS Host Channel-4 Characteristics Register" hgroup.long (0x580+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT4,OTG_HS Host Channel-4 Split Control Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT4,OTG_HS Host Channel-4 Interrupt Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK4,OTG_HS Host Channel-4 Interrupt Mask Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ4,OTG_HS Host Channel-4 Transfer Size Register" hgroup.long (0x580+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA4,OTG_HS Host Channel-4 DMA Address Register" hgroup.long 0x5A0++0x03 hide.long 0x00 "OTG_HS_HCCHAR5,OTG_HS Host Channel-5 Characteristics Register" hgroup.long (0x5A0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT5,OTG_HS Host Channel-5 Split Control Register" hgroup.long (0x5A0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT5,OTG_HS Host Channel-5 Interrupt Register" hgroup.long (0x5A0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK5,OTG_HS Host Channel-5 Interrupt Mask Register" hgroup.long (0x5A0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ5,OTG_HS Host Channel-5 Transfer Size Register" hgroup.long (0x5A0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA5,OTG_HS Host Channel-5 DMA Address Register" hgroup.long 0x5C0++0x03 hide.long 0x00 "OTG_HS_HCCHAR6,OTG_HS Host Channel-6 Characteristics Register" hgroup.long (0x5C0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT6,OTG_HS Host Channel-6 Split Control Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT6,OTG_HS Host Channel-6 Interrupt Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK6,OTG_HS Host Channel-6 Interrupt Mask Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ6,OTG_HS Host Channel-6 Transfer Size Register" hgroup.long (0x5C0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA6,OTG_HS Host Channel-6 DMA Address Register" hgroup.long 0x5E0++0x03 hide.long 0x00 "OTG_HS_HCCHAR7,OTG_HS Host Channel-7 Characteristics Register" hgroup.long (0x5E0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT7,OTG_HS Host Channel-7 Split Control Register" hgroup.long (0x5E0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT7,OTG_HS Host Channel-7 Interrupt Register" hgroup.long (0x5E0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK7,OTG_HS Host Channel-7 Interrupt Mask Register" hgroup.long (0x5E0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ7,OTG_HS Host Channel-7 Transfer Size Register" hgroup.long (0x5E0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA7,OTG_HS Host Channel-7 DMA Address Register" hgroup.long 0x600++0x03 hide.long 0x00 "OTG_HS_HCCHAR8,OTG_HS Host Channel-8 Characteristics Register" hgroup.long (0x600+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT8,OTG_HS Host Channel-8 Split Control Register" hgroup.long (0x600+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT8,OTG_HS Host Channel-8 Interrupt Register" hgroup.long (0x600+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK8,OTG_HS Host Channel-8 Interrupt Mask Register" hgroup.long (0x600+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ8,OTG_HS Host Channel-8 Transfer Size Register" hgroup.long (0x600+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA8,OTG_HS Host Channel-8 DMA Address Register" hgroup.long 0x620++0x03 hide.long 0x00 "OTG_HS_HCCHAR9,OTG_HS Host Channel-9 Characteristics Register" hgroup.long (0x620+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT9,OTG_HS Host Channel-9 Split Control Register" hgroup.long (0x620+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT9,OTG_HS Host Channel-9 Interrupt Register" hgroup.long (0x620+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK9,OTG_HS Host Channel-9 Interrupt Mask Register" hgroup.long (0x620+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ9,OTG_HS Host Channel-9 Transfer Size Register" hgroup.long (0x620+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA9,OTG_HS Host Channel-9 DMA Address Register" hgroup.long 0x640++0x03 hide.long 0x00 "OTG_HS_HCCHAR10,OTG_HS Host Channel-10 Characteristics Register" hgroup.long (0x640+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT10,OTG_HS Host Channel-10 Split Control Register" hgroup.long (0x640+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT10,OTG_HS Host Channel-10 Interrupt Register" hgroup.long (0x640+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK10,OTG_HS Host Channel-10 Interrupt Mask Register" hgroup.long (0x640+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ10,OTG_HS Host Channel-10 Transfer Size Register" hgroup.long (0x640+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA10,OTG_HS Host Channel-10 DMA Address Register" hgroup.long 0x660++0x03 hide.long 0x00 "OTG_HS_HCCHAR11,OTG_HS Host Channel-11 Characteristics Register" hgroup.long (0x660+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT11,OTG_HS Host Channel-11 Split Control Register" hgroup.long (0x660+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT11,OTG_HS Host Channel-11 Interrupt Register" hgroup.long (0x660+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK11,OTG_HS Host Channel-11 Interrupt Mask Register" hgroup.long (0x660+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ11,OTG_HS Host Channel-11 Transfer Size Register" hgroup.long (0x660+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA11,OTG_HS Host Channel-11 DMA Address Register" hgroup.long 0x680++0x03 hide.long 0x00 "OTG_HS_HCCHAR12,OTG_HS Host Channel-12 Characteristics Register" hgroup.long (0x680+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT12,OTG_HS Host Channel-12 Split Control Register" hgroup.long (0x680+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT12,OTG_HS Host Channel-12 Interrupt Register" hgroup.long (0x680+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK12,OTG_HS Host Channel-12 Interrupt Mask Register" hgroup.long (0x680+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ12,OTG_HS Host Channel-12 Transfer Size Register" hgroup.long (0x680+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA12,OTG_HS Host Channel-12 DMA Address Register" hgroup.long 0x6A0++0x03 hide.long 0x00 "OTG_HS_HCCHAR13,OTG_HS Host Channel-13 Characteristics Register" hgroup.long (0x6A0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT13,OTG_HS Host Channel-13 Split Control Register" hgroup.long (0x6A0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT13,OTG_HS Host Channel-13 Interrupt Register" hgroup.long (0x6A0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK13,OTG_HS Host Channel-13 Interrupt Mask Register" hgroup.long (0x6A0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ13,OTG_HS Host Channel-13 Transfer Size Register" hgroup.long (0x6A0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA13,OTG_HS Host Channel-13 DMA Address Register" hgroup.long 0x6C0++0x03 hide.long 0x00 "OTG_HS_HCCHAR14,OTG_HS Host Channel-14 Characteristics Register" hgroup.long (0x6C0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT14,OTG_HS Host Channel-14 Split Control Register" hgroup.long (0x6C0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT14,OTG_HS Host Channel-14 Interrupt Register" hgroup.long (0x6C0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK14,OTG_HS Host Channel-14 Interrupt Mask Register" hgroup.long (0x6C0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ14,OTG_HS Host Channel-14 Transfer Size Register" hgroup.long (0x6C0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA14,OTG_HS Host Channel-14 DMA Address Register" hgroup.long 0x6E0++0x03 hide.long 0x00 "OTG_HS_HCCHAR15,OTG_HS Host Channel-15 Characteristics Register" hgroup.long (0x6E0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT15,OTG_HS Host Channel-15 Split Control Register" hgroup.long (0x6E0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT15,OTG_HS Host Channel-15 Interrupt Register" hgroup.long (0x6E0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK15,OTG_HS Host Channel-15 Interrupt Mask Register" hgroup.long (0x6E0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ15,OTG_HS Host Channel-15 Transfer Size Register" hgroup.long (0x6E0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA15,OTG_HS Host Channel-15 DMA Address Register" else hgroup.long 0x500++0x03 hide.long 0x00 "OTG_HS_HCCHAR0,OTG_HS Host Channel-0 Characteristics Register" hgroup.long (0x500+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT0,OTG_HS Host Channel-0 Split Control Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT0,OTG_HS Host Channel-0 Interrupt Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK0,OTG_HS Host Channel-0 Interrupt Mask Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ0,OTG_HS Host Channel-0 Transfer Size Register" hgroup.long (0x500+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA0,OTG_HS Host Channel-0 DMA Address Register" hgroup.long 0x520++0x03 hide.long 0x00 "OTG_HS_HCCHAR1,OTG_HS Host Channel-1 Characteristics Register" hgroup.long (0x520+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT1,OTG_HS Host Channel-1 Split Control Register" hgroup.long (0x520+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT1,OTG_HS Host Channel-1 Interrupt Register" hgroup.long (0x520+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK1,OTG_HS Host Channel-1 Interrupt Mask Register" hgroup.long (0x520+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ1,OTG_HS Host Channel-1 Transfer Size Register" hgroup.long (0x520+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA1,OTG_HS Host Channel-1 DMA Address Register" hgroup.long 0x540++0x03 hide.long 0x00 "OTG_HS_HCCHAR2,OTG_HS Host Channel-2 Characteristics Register" hgroup.long (0x540+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT2,OTG_HS Host Channel-2 Split Control Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT2,OTG_HS Host Channel-2 Interrupt Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK2,OTG_HS Host Channel-2 Interrupt Mask Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ2,OTG_HS Host Channel-2 Transfer Size Register" hgroup.long (0x540+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA2,OTG_HS Host Channel-2 DMA Address Register" hgroup.long 0x560++0x03 hide.long 0x00 "OTG_HS_HCCHAR3,OTG_HS Host Channel-3 Characteristics Register" hgroup.long (0x560+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT3,OTG_HS Host Channel-3 Split Control Register" hgroup.long (0x560+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT3,OTG_HS Host Channel-3 Interrupt Register" hgroup.long (0x560+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK3,OTG_HS Host Channel-3 Interrupt Mask Register" hgroup.long (0x560+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ3,OTG_HS Host Channel-3 Transfer Size Register" hgroup.long (0x560+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA3,OTG_HS Host Channel-3 DMA Address Register" hgroup.long 0x580++0x03 hide.long 0x00 "OTG_HS_HCCHAR4,OTG_HS Host Channel-4 Characteristics Register" hgroup.long (0x580+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT4,OTG_HS Host Channel-4 Split Control Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT4,OTG_HS Host Channel-4 Interrupt Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK4,OTG_HS Host Channel-4 Interrupt Mask Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ4,OTG_HS Host Channel-4 Transfer Size Register" hgroup.long (0x580+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA4,OTG_HS Host Channel-4 DMA Address Register" hgroup.long 0x5A0++0x03 hide.long 0x00 "OTG_HS_HCCHAR5,OTG_HS Host Channel-5 Characteristics Register" hgroup.long (0x5A0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT5,OTG_HS Host Channel-5 Split Control Register" hgroup.long (0x5A0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT5,OTG_HS Host Channel-5 Interrupt Register" hgroup.long (0x5A0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK5,OTG_HS Host Channel-5 Interrupt Mask Register" hgroup.long (0x5A0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ5,OTG_HS Host Channel-5 Transfer Size Register" hgroup.long (0x5A0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA5,OTG_HS Host Channel-5 DMA Address Register" hgroup.long 0x5C0++0x03 hide.long 0x00 "OTG_HS_HCCHAR6,OTG_HS Host Channel-6 Characteristics Register" hgroup.long (0x5C0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT6,OTG_HS Host Channel-6 Split Control Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT6,OTG_HS Host Channel-6 Interrupt Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK6,OTG_HS Host Channel-6 Interrupt Mask Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ6,OTG_HS Host Channel-6 Transfer Size Register" hgroup.long (0x5C0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA6,OTG_HS Host Channel-6 DMA Address Register" hgroup.long 0x5E0++0x03 hide.long 0x00 "OTG_HS_HCCHAR7,OTG_HS Host Channel-7 Characteristics Register" hgroup.long (0x5E0+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT7,OTG_HS Host Channel-7 Split Control Register" hgroup.long (0x5E0+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT7,OTG_HS Host Channel-7 Interrupt Register" hgroup.long (0x5E0+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK7,OTG_HS Host Channel-7 Interrupt Mask Register" hgroup.long (0x5E0+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ7,OTG_HS Host Channel-7 Transfer Size Register" hgroup.long (0x5E0+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA7,OTG_HS Host Channel-7 DMA Address Register" hgroup.long 0x600++0x03 hide.long 0x00 "OTG_HS_HCCHAR8,OTG_HS Host Channel-8 Characteristics Register" hgroup.long (0x600+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT8,OTG_HS Host Channel-8 Split Control Register" hgroup.long (0x600+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT8,OTG_HS Host Channel-8 Interrupt Register" hgroup.long (0x600+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK8,OTG_HS Host Channel-8 Interrupt Mask Register" hgroup.long (0x600+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ8,OTG_HS Host Channel-8 Transfer Size Register" hgroup.long (0x600+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA8,OTG_HS Host Channel-8 DMA Address Register" hgroup.long 0x620++0x03 hide.long 0x00 "OTG_HS_HCCHAR9,OTG_HS Host Channel-9 Characteristics Register" hgroup.long (0x620+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT9,OTG_HS Host Channel-9 Split Control Register" hgroup.long (0x620+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT9,OTG_HS Host Channel-9 Interrupt Register" hgroup.long (0x620+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK9,OTG_HS Host Channel-9 Interrupt Mask Register" hgroup.long (0x620+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ9,OTG_HS Host Channel-9 Transfer Size Register" hgroup.long (0x620+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA9,OTG_HS Host Channel-9 DMA Address Register" hgroup.long 0x640++0x03 hide.long 0x00 "OTG_HS_HCCHAR10,OTG_HS Host Channel-10 Characteristics Register" hgroup.long (0x640+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT10,OTG_HS Host Channel-10 Split Control Register" hgroup.long (0x640+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT10,OTG_HS Host Channel-10 Interrupt Register" hgroup.long (0x640+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK10,OTG_HS Host Channel-10 Interrupt Mask Register" hgroup.long (0x640+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ10,OTG_HS Host Channel-10 Transfer Size Register" hgroup.long (0x640+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA10,OTG_HS Host Channel-10 DMA Address Register" hgroup.long 0x660++0x03 hide.long 0x00 "OTG_HS_HCCHAR11,OTG_HS Host Channel-11 Characteristics Register" hgroup.long (0x660+0x04)++0x03 hide.long 0x00 "OTG_HS_HCSPLT11,OTG_HS Host Channel-11 Split Control Register" hgroup.long (0x660+0x08)++0x03 hide.long 0x00 "OTG_HS_HCINT11,OTG_HS Host Channel-11 Interrupt Register" hgroup.long (0x660+0x0C)++0x03 hide.long 0x00 "OTG_HS_HCINTMSK11,OTG_HS Host Channel-11 Interrupt Mask Register" hgroup.long (0x660+0x10)++0x03 hide.long 0x00 "OTG_HS_HCTSIZ11,OTG_HS Host Channel-11 Transfer Size Register" hgroup.long (0x660+0x14)++0x03 hide.long 0x00 "OTG_HS_HCDMA11,OTG_HS Host Channel-11 DMA Address Register" endif endif tree.end width 21. tree "Device mode registers" group.long 0x800++0x07 line.long 0x00 "OTG_HS_DCFG,OTG_HS Device Configuration Register" bitfld.long 0x00 24.--25. " PERSCHIVL ,Periodic scheduling interval" "25%,50%,75%,?..." sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") textline " " bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Not masked,Masked" endif textline " " bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%" textline " " hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address" bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "NAK and STALL,STALL" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 0.--1. " DSPD ,Device speed" ",,,Full" else bitfld.long 0x00 0.--1. " DSPD ,Device speed" "High,Full (external),,Full (internal)" endif line.long 0x04 "OTG_HS_DCTL,OTG_HS Device Control Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected" textline " " endif bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done" "Not done,Done" bitfld.long 0x04 10. " CGONAK ,Clear global OUT NAK" "No effect,Clear" textline " " bitfld.long 0x04 9. " SGONAK ,Set global OUT NAK" "No effect,Set" bitfld.long 0x04 8. " CGINAK ,Clear global IN NAK" "No effect,Clear" textline " " bitfld.long 0x04 7. " SGINAK ,Set global IN NAK" "No effect,Set" bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..." textline " " rbitfld.long 0x04 3. " GONSTS ,Global OUT NAK status" "Sent NAK and STALL,Sent a NAK" textline " " rbitfld.long 0x04 2. " GINSTS ,Global IN NAK status" "Handshake is sent,Handshake is sent out" textline " " bitfld.long 0x04 1. " SDIS ,Soft disconnect" "Connected,Not connected" bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "Suspended,Not suspended" rgroup.long 0x808++0x03 line.long 0x00 "OTG_HS_DSTS,OTG_HS Device Status Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 23. " DEVLNSTS_D+ ,Device line status - logic level of D+" "Low,High" bitfld.long 0x00 22. " DEVLNSTS_D- ,Device line status - logic level of D-" "Low,High" textline " " endif hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF" bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error" textline " " sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full" else bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" "High,,,Full" endif textline " " bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended" group.long 0x810++0x07 line.long 0x00 "OTG_HS_DIEPMSK,OTG_HS Device IN Endpoint Common Interrupt Mask Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked" textline " " endif bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked" bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked" textline " " bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked" bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked" textline " " bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked" bitfld.long 0x00 3. " TOM ,Timeout condition mask" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" line.long 0x04 "OTG_HS_DOEPMSK,OTG_HS Device OUT Endpoint Common Interrupt Mask Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 14. " NYET ,NYET interrupt mask for USB OTG HS" "Masked,Unmasked" textline " " endif bitfld.long 0x04 9. " BOIM ,BNA interrupt mask" "Masked,Unmasked" sif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.long 0x04 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked" else bitfld.long 0x04 8. " OPEM ,OUT packet error mask" "Masked,Unmasked" endif textline " " bitfld.long 0x04 6. " B2BSTUP , Back-to-back SETUP packets received mask" "Masked,Unmasked" bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked" textline " " bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked" bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" rgroup.long 0x818++0x03 line.long 0x00 "OTG_HS_DAINT,OTG_HS Device All Endpoints Interrupt Register" bitfld.long 0x00 31. " OEPINT[15] ,OUT endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 30. " OEPINT[14] ,OUT endpoint interrupt bit 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " OEPINT[13] ,OUT endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 28. " OEPINT[12] ,OUT endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " OEPINT[11] ,OUT endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 26. " OEPINT[10] ,OUT endpoint interrupt bit 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " OEPINT[9] ,OUT endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 24. " OEPINT[8] ,OUT endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " OEPINT[7] ,OUT endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 22. " OEPINT[6] ,OUT endpoint interrupt bit 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " OEPINT[5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 20. " OEPINT[4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " OEPINT[3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 18. " OEPINT[2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " OEPINT[1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 16. " OEPINT[0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IEPINT[15] ,IN endpoint interrupt bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " IEPINT[14] ,IN endpoint interrupt bit 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " IEPINT[13] ,IN endpoint interrupt bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " IEPINT[12] ,IN endpoint interrupt bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IEPINT[11] ,IN endpoint interrupt bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " IEPINT[10] ,IN endpoint interrupt bit 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " IEPINT[9] ,IN endpoint interrupt bit 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " IEPINT[8] ,IN endpoint interrupt bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IEPINT[7] ,IN endpoint interrupt bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " IEPINT[6] ,IN endpoint interrupt bit 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " IEPINT[5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " IEPINT[4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IEPINT[3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " IEPINT[2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " IEPINT[1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " IEPINT[0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt" group.long 0x81C++0x03 line.long 0x00 "OTG_HS_DAINTMSK,OTG_HS All Endpoints Interrupt Mask Register" bitfld.long 0x00 31. " OEPM[15] ,OUT EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 30. " OEPM[14] ,OUT EP interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 29. " OEPM[13] ,OUT EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 28. " OEPM[12] ,OUT EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 27. " OEPM[11] ,OUT EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 26. " OEPM[10] ,OUT EP interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 25. " OEPM[9] ,OUT EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 24. " OEPM[8] ,OUT EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 23. " OEPM[7] ,OUT EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 22. " OEPM[6] ,OUT EP interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 21. " OEPM[5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 20. " OEPM[4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 19. " OEPM[3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 18. " OEPM[2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 17. " OEPM[1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 16. " OEPM[0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked" textline " " bitfld.long 0x00 15. " IEPM[15] ,IN EP interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " IEPM[14] ,IN EP interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " IEPM[13] ,IN EP interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " IEPM[12] ,IN EP interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " IEPM[11] ,IN EP interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " IEPM[10] ,IN EP interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " IEPM[9] ,IN EP interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " IEPM[8] ,IN EP interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " IEPM[7] ,IN EP interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " IEPM[6] ,IN EP interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " IEPM[5] ,IN EP interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " IEPM[4] ,IN EP interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " IEPM[3] ,IN EP interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " IEPM[2] ,IN EP interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " IEPM[1] ,IN EP interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " IEPM[0] ,IN EP interrupt mask bit 0" "Masked,Unmasked" group.long 0x828++0x0B line.long 0x00 "OTG_HS_DVBUSDIS,OTG_HS Device VBUS Discharge Time Register" hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time" line.long 0x04 "OTG_HS_DVBUSPULSE,OTG_HS Device VBUS Pulsing Time Register" hexmask.long.word 0x04 0.--11. 1. " DVBUSP ,Device VBUS pulsing time" line.long 0x08 "OTG_HS_DTHRCTL,OTG_HS Device Threshold Control Register" bitfld.long 0x08 27. " ARPEN ,Arbiter parking enable" "Disabled,Enabled" hexmask.long.word 0x08 17.--25. 1. " RXTHRLEN ,Receive threshold length" textline " " bitfld.long 0x08 16. " RXTHREN ,Receive threshold enable" "Disabled,Enabled" hexmask.long.word 0x08 2.--10. 1. " TXTHRLEN ,Transmit threshold length" textline " " bitfld.long 0x08 1. " ISOTHREN ,Isochronous IN endpoint threshold enable" "Disabled,Enabled" bitfld.long 0x08 0. " NONISOTHREN ,Nonisochronous IN endpoints threshold enable" "Disabled,Enabled" group.long 0x834++0x0B line.long 0x00 "OTG_HS_DIEPEMPMSK,OTG_HS Device IN Endpoint FIFO Empty Interrupt Mask Register" bitfld.long 0x00 15. " INEPTXFEM[15] ,IN EP Tx FIFO empty interrupt mask bit 15" "Masked,Unmasked" bitfld.long 0x00 14. " INEPTXFEM[14] ,IN EP Tx FIFO empty interrupt mask bit 14" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " INEPTXFEM[13] ,IN EP Tx FIFO empty interrupt mask bit 13" "Masked,Unmasked" bitfld.long 0x00 12. " INEPTXFEM[12] ,IN EP Tx FIFO empty interrupt mask bit 12" "Masked,Unmasked" textline " " bitfld.long 0x00 11. " INEPTXFEM[11] ,IN EP Tx FIFO empty interrupt mask bit 11" "Masked,Unmasked" bitfld.long 0x00 10. " INEPTXFEM[10] ,IN EP Tx FIFO empty interrupt mask bit 10" "Masked,Unmasked" textline " " bitfld.long 0x00 9. " INEPTXFEM[9] ,IN EP Tx FIFO empty interrupt mask bit 9" "Masked,Unmasked" bitfld.long 0x00 8. " INEPTXFEM[8] ,IN EP Tx FIFO empty interrupt mask bit 8" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " INEPTXFEM[7] ,IN EP Tx FIFO empty interrupt mask bit 7" "Masked,Unmasked" bitfld.long 0x00 6. " INEPTXFEM[6] ,IN EP Tx FIFO empty interrupt mask bit 6" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " INEPTXFEM[5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked" bitfld.long 0x00 4. " INEPTXFEM[4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " INEPTXFEM[3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked" bitfld.long 0x00 2. " INEPTXFEM[2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " INEPTXFEM[1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked" bitfld.long 0x00 0. " INEPTXFEM[0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked" line.long 0x04 "OTG_HS_DEACHINT,OTG_HS Device Each Endpoint Interrupt Register" bitfld.long 0x04 17. " OEP1INT ,OUT endpoint 1 interrupt bit" "0,1" textline " " bitfld.long 0x04 1. " IEP1INT ,IN endpoint 1interrupt bit" "0,1" sif cpuis("STM32F469*")||cpuis("STM32F479*") line.long 0x08 "OTG_DEACHINTMSK,OTG Device Each Endpoint Interrupt Register Mask" bitfld.long 0x08 17. " OEP1INTM ,OUT endpoint 1 interrupt mask bit" "0,1" textline " " bitfld.long 0x08 1. " IEP1INTM ,IN endpoint 1 interrupt mask bit" "0,1" else line.long 0x08 "OTG_HS_DEACHINT,OTG_HS Device Each Endpoint Interrupt Register" bitfld.long 0x08 17. " OEP1INTM ,OUT endpoint 1 interrupt bit" "0,1" textline " " bitfld.long 0x08 1. " IEP1INTM ,IN endpoint 1interrupt bit" "0,1" endif sif !cpuis("STM32F446*") group.long 0x880++0x03 line.long 0x00 "OTG_HS_DIEPEACHMSK1,OTG_HS Device Each IN Endpoint-1 Interrupt Register" bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked" bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked" bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked" textline " " bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked" bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked" textline " " bitfld.long 0x00 3. " TOM ,Timeout condition mask (nonisochronous endpoints)" "Masked,Unmasked" bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" group.long 0x884++0x3 line.long 0x00 "OTG_HS_DOEPEACHMSK1,OTG_HS Device Each OUT Endpoint-1 Interrupt Register" bitfld.long 0x00 14. " NYETM ,NYET interrupt mask" "Masked,Unmasked" bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 12. " BERRM ,Bubble error interrupt mask" "Masked,Unmasked" bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked" textline " " bitfld.long 0x00 8. " OPEM ,OUT packet error mask" "Masked,Unmasked" bitfld.long 0x00 2. " AHBERRM ,AHB error mask" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked" bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked" endif group.long 0x900++0x03 line.long 0x00 "OTG_HS_DIEPCTL0,OTG_HS Device Control IN Endpoint 0 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "Not received,Received" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK,NAK" textline " " rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x40040000+0x920))&0xC0000)==0x40000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0x80000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0xC0000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x940))&0xC0000)==0x40000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0x80000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0xC0000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x960))&0xC0000)==0x40000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0x80000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0xC0000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x980))&0xC0000)==0x40000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0x80000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0xC0000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x40000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x80000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0xC0000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x40000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x80000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0xC0000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x40000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x80000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0xC0000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x40000) group.long 0xA00++0x03 line.long 0x00 "OTG_HS_DIEPCTL8,OTG Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0x80000) group.long 0xA00++0x03 line.long 0x00 "OTG_HS_DIEPCTL8,OTG Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xA00))&0xC0000)==0xC0000) group.long 0xA00++0x03 line.long 0x00 "OTG_HS_DIEPCTL8,OTG Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xA00++0x03 line.long 0x00 "OTG_HS_DIEPCTL8,OTG Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif else if (((per.l(ad:0x40040000+0x920))&0xC0000)==0x40000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0x80000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x920))&0xC0000)==0xC0000) group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x920++0x03 line.long 0x00 "OTG_HS_DIEPCTL1,OTG Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x940))&0xC0000)==0x40000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0x80000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x940))&0xC0000)==0xC0000) group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x940++0x03 line.long 0x00 "OTG_HS_DIEPCTL2,OTG Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x960))&0xC0000)==0x40000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0x80000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x960))&0xC0000)==0xC0000) group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x960++0x03 line.long 0x00 "OTG_HS_DIEPCTL3,OTG Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x980))&0xC0000)==0x40000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0x80000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x980))&0xC0000)==0xC0000) group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x980++0x03 line.long 0x00 "OTG_HS_DIEPCTL4,OTG Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x40000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0x80000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9A0))&0xC0000)==0xC0000) group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9A0++0x03 line.long 0x00 "OTG_HS_DIEPCTL5,OTG Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x40000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0x80000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9C0))&0xC0000)==0xC0000) group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9C0++0x03 line.long 0x00 "OTG_HS_DIEPCTL6,OTG Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x40000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0x80000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0x9E0))&0xC0000)==0xC0000) group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0x9E0++0x03 line.long 0x00 "OTG_HS_DIEPCTL7,OTG Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No effect,Disabled" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif group.long 0xB00++0x03 line.long 0x00 "OTG_HS_DOEPCTL0,OTG_HS Device Control OUT Endpoint 0 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" sif cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" else bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" endif textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..." rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " sif cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes" else bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes" endif sif cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x40000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x80000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0xC0000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x40000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x80000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0xC0000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x40000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x80000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0xC0000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x40000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x80000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0xC0000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x40000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x80000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0xC0000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x40000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x80000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0xC0000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x40000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x80000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0xC0000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x40000) group.long 0xC00++0x03 line.long 0x00 "OTG_HS_DOEPCTL8,OTG_HS Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0x80000) group.long 0xC00++0x03 line.long 0x00 "OTG_HS_DOEPCTL8,OTG_HS Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xC00))&0xC0000)==0xC0000) group.long 0xC00++0x03 line.long 0x00 "OTG_HS_DOEPCTL8,OTG_HS Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SD1PID ,Set DATA1 PID" "DATA0,DATA1" bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" textline " " hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xC00++0x03 line.long 0x00 "OTG_HS_DOEPCTL8,OTG_HS Device Endpoint-8 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif elif cpuis("STM32F446*") if (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x40000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x80000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0xC0000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x40000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x80000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0xC0000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x40000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x80000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0xC0000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x40000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0x80000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB80))&0xC0000)==0xC0000) group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB80++0x03 line.long 0x00 "OTG_HS_DOEPCTL4,OTG_HS Device Endpoint-4 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x40000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0x80000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBA0))&0xC0000)==0xC0000) group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBA0++0x03 line.long 0x00 "OTG_HS_DOEPCTL5,OTG_HS Device Endpoint-5 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x40000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0x80000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBC0))&0xC0000)==0xC0000) group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBC0++0x03 line.long 0x00 "OTG_HS_DOEPCTL6,OTG_HS Device Endpoint-6 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x40000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0x80000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xBE0))&0xC0000)==0xC0000) group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xBE0++0x03 line.long 0x00 "OTG_HS_DOEPCTL7,OTG_HS Device Endpoint-7 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif else if (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x40000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0x80000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB20))&0xC0000)==0xC0000) group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB20++0x03 line.long 0x00 "OTG_HS_DOEPCTL1,OTG_HS Device Endpoint-1 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x40000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0x80000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB40))&0xC0000)==0xC0000) group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB40++0x03 line.long 0x00 "OTG_HS_DOEPCTL2,OTG_HS Device Endpoint-2 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif if (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x40000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd" bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0x80000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" elif (((per.l(ad:0x40040000+0xB60))&0xC0000)==0xC0000) group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0" bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" textline " " bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" textline " " bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" textline " " rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" else group.long 0xB60++0x03 line.long 0x00 "OTG_HS_DOEPCTL3,OTG_HS Device Endpoint-3 Control Register" bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled" bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes" textline " " bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set" bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear" textline " " bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set" bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt" rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK" textline " " bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active" hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size" endif endif sif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x908++0x03 line.long 0x00 "OTG_HS_DIEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x928++0x03 line.long 0x00 "OTG_HS_DIEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x948++0x03 line.long 0x00 "OTG_HS_DIEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x968++0x03 line.long 0x00 "OTG_HS_DIEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x988++0x03 line.long 0x00 "OTG_HS_DIEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9A8++0x03 line.long 0x00 "OTG_HS_DIEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9C8++0x03 line.long 0x00 "OTG_HS_DIEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9E8++0x03 line.long 0x00 "OTG_HS_DIEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0xA08++0x03 line.long 0x00 "OTG_HS_DIEPINT8,OTG_HS Device Endpoint-8 Interrupt Register" eventfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" eventfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " TXFIFOUDRN ,Transmit FIFO underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0x908++0x03 line.long 0x00 "OTG_HS_DIEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x928++0x03 line.long 0x00 "OTG_HS_DIEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x948++0x03 line.long 0x00 "OTG_HS_DIEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x968++0x03 line.long 0x00 "OTG_HS_DIEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x988++0x03 line.long 0x00 "OTG_HS_DIEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9A8++0x03 line.long 0x00 "OTG_HS_DIEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9C8++0x03 line.long 0x00 "OTG_HS_DIEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" group.long 0x9E8++0x03 line.long 0x00 "OTG_HS_DIEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" bitfld.long 0x00 13. " NAK ,NAK interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " BERR ,Babble error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PKTDRPSTS ,Packet dropped status" "Not dropped,Dropped" bitfld.long 0x00 9. " BNA ,Buffer not available interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " TXFIFOUDRN ,Transmit Fifo Underrun interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty" textline " " eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt" eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif sif cpuis("STM32F469*")||cpuis("STM32F479*") if ((per.l(ad:0x40040000+0xB08-0x08)&0xC0000)==0x00) group.long 0xB08++0x03 line.long 0x00 "OTG_HS_DOEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB08++0x03 line.long 0x00 "OTG_HS_DOEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB28-0x08)&0xC0000)==0x00) group.long 0xB28++0x03 line.long 0x00 "OTG_HS_DOEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB28++0x03 line.long 0x00 "OTG_HS_DOEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB48-0x08)&0xC0000)==0x00) group.long 0xB48++0x03 line.long 0x00 "OTG_HS_DOEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB48++0x03 line.long 0x00 "OTG_HS_DOEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB68-0x08)&0xC0000)==0x00) group.long 0xB68++0x03 line.long 0x00 "OTG_HS_DOEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB68++0x03 line.long 0x00 "OTG_HS_DOEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB88-0x08)&0xC0000)==0x00) group.long 0xB88++0x03 line.long 0x00 "OTG_HS_DOEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB88++0x03 line.long 0x00 "OTG_HS_DOEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBA8-0x08)&0xC0000)==0x00) group.long 0xBA8++0x03 line.long 0x00 "OTG_HS_DOEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBA8++0x03 line.long 0x00 "OTG_HS_DOEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBC8-0x08)&0xC0000)==0x00) group.long 0xBC8++0x03 line.long 0x00 "OTG_HS_DOEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBC8++0x03 line.long 0x00 "OTG_HS_DOEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBE8-0x08)&0xC0000)==0x00) group.long 0xBE8++0x03 line.long 0x00 "OTG_HS_DOEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBE8++0x03 line.long 0x00 "OTG_HS_DOEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xC08-0x08)&0xC0000)==0x00) group.long 0xC08++0x03 line.long 0x00 "OTG_HS_DOEPINT8,OTG_HS Device Endpoint-8 Interrupt Register" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xC08++0x03 line.long 0x00 "OTG_HS_DOEPINT8,OTG_HS Device Endpoint-8 Interrupt Register" eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif else if ((per.l(ad:0x40040000+0xB08-0x08)&0xC0000)==0x00) group.long 0xB08++0x03 line.long 0x00 "OTG_HS_DOEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB08++0x03 line.long 0x00 "OTG_HS_DOEPINT0,OTG_HS Device Endpoint-0 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB28-0x08)&0xC0000)==0x00) group.long 0xB28++0x03 line.long 0x00 "OTG_HS_DOEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB28++0x03 line.long 0x00 "OTG_HS_DOEPINT1,OTG_HS Device Endpoint-1 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB48-0x08)&0xC0000)==0x00) group.long 0xB48++0x03 line.long 0x00 "OTG_HS_DOEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB48++0x03 line.long 0x00 "OTG_HS_DOEPINT2,OTG_HS Device Endpoint-2 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB68-0x08)&0xC0000)==0x00) group.long 0xB68++0x03 line.long 0x00 "OTG_HS_DOEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB68++0x03 line.long 0x00 "OTG_HS_DOEPINT3,OTG_HS Device Endpoint-3 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xB88-0x08)&0xC0000)==0x00) group.long 0xB88++0x03 line.long 0x00 "OTG_HS_DOEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xB88++0x03 line.long 0x00 "OTG_HS_DOEPINT4,OTG_HS Device Endpoint-4 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBA8-0x08)&0xC0000)==0x00) group.long 0xBA8++0x03 line.long 0x00 "OTG_HS_DOEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBA8++0x03 line.long 0x00 "OTG_HS_DOEPINT5,OTG_HS Device Endpoint-5 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBC8-0x08)&0xC0000)==0x00) group.long 0xBC8++0x03 line.long 0x00 "OTG_HS_DOEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBC8++0x03 line.long 0x00 "OTG_HS_DOEPINT6,OTG_HS Device Endpoint-6 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif if ((per.l(ad:0x40040000+0xBE8-0x08)&0xC0000)==0x00) group.long 0xBE8++0x03 line.long 0x00 "OTG_HS_DOEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received" textline " " eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt" eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" else group.long 0xBE8++0x03 line.long 0x00 "OTG_HS_DOEPINT7,OTG_HS Device Endpoint-7 Interrupt Register" bitfld.long 0x00 14. " NYET ,NYET interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed" endif endif textline " " group.long 0x910++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ0,OTG_HS Device IN Endpoint 0 Transfer Size Register" bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" sif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x914++0x03 line.long 0x00 "OTG_DIEPDMA0,OTG Device Channel-0 DMA Address Register" group.long 0x934++0x03 line.long 0x00 "OTG_DIEPDMA1,OTG Device Channel-1 DMA Address Register" group.long 0x954++0x03 line.long 0x00 "OTG_DIEPDMA2,OTG Device Channel-2 DMA Address Register" group.long 0x974++0x03 line.long 0x00 "OTG_DIEPDMA3,OTG Device Channel-3 DMA Address Register" group.long 0x994++0x03 line.long 0x00 "OTG_DIEPDMA4,OTG Device Channel-4 DMA Address Register" group.long 0x9B4++0x03 line.long 0x00 "OTG_DIEPDMA5,OTG Device Channel-5 DMA Address Register" group.long 0x9D4++0x03 line.long 0x00 "OTG_DIEPDMA6,OTG Device Channel-6 DMA Address Register" group.long 0x9F4++0x03 line.long 0x00 "OTG_DIEPDMA7,OTG Device Channel-7 DMA Address Register" group.long 0xA14++0x03 line.long 0x00 "OTG_DIEPDMA8,OTG Device Channel-8 DMA Address Register" group.long 0xA34++0x03 line.long 0x00 "OTG_DIEPDMA9,OTG Device Channel-9 DMA Address Register" group.long 0xA54++0x03 line.long 0x00 "OTG_DIEPDMA10,OTG Device Channel-10 DMA Address Register" group.long 0xA74++0x03 line.long 0x00 "OTG_DIEPDMA11,OTG Device Channel-11 DMA Address Register" group.long 0xA94++0x03 line.long 0x00 "OTG_DIEPDMA12,OTG Device Channel-12 DMA Address Register" group.long 0xAB4++0x03 line.long 0x00 "OTG_DIEPDMA13,OTG Device Channel-13 DMA Address Register" group.long 0xAD4++0x03 line.long 0x00 "OTG_DIEPDMA14,OTG Device Channel-14 DMA Address Register" group.long 0xAF4++0x03 line.long 0x00 "OTG_DIEPDMA15,OTG Device Channel-15 DMA Address Register" group.long 0xB14++0x03 line.long 0x00 "OTG_DOEPDMA0,OTG Device Channel-0 DMA Address Register" group.long 0xB34++0x03 line.long 0x00 "OTG_DOEPDMA1,OTG Device Channel-1 DMA Address Register" group.long 0xB54++0x03 line.long 0x00 "OTG_DOEPDMA2,OTG Device Channel-2 DMA Address Register" group.long 0xB74++0x03 line.long 0x00 "OTG_DOEPDMA3,OTG Device Channel-3 DMA Address Register" group.long 0xB94++0x03 line.long 0x00 "OTG_DOEPDMA4,OTG Device Channel-4 DMA Address Register" group.long 0xBB4++0x03 line.long 0x00 "OTG_DOEPDMA5,OTG Device Channel-5 DMA Address Register" group.long 0xBD4++0x03 line.long 0x00 "OTG_DOEPDMA6,OTG Device Channel-6 DMA Address Register" group.long 0xBF4++0x03 line.long 0x00 "OTG_DOEPDMA7,OTG Device Channel-7 DMA Address Register" group.long 0xC14++0x03 line.long 0x00 "OTG_DOEPDMA8,OTG Device Channel-8 DMA Address Register" group.long 0xC34++0x03 line.long 0x00 "OTG_DOEPDMA9,OTG Device Channel-9 DMA Address Register" group.long 0xC54++0x03 line.long 0x00 "OTG_DOEPDMA10,OTG Device Channel-10 DMA Address Register" group.long 0xC74++0x03 line.long 0x00 "OTG_DOEPDMA11,OTG Device Channel-11 DMA Address Register" group.long 0xC94++0x03 line.long 0x00 "OTG_DOEPDMA12,OTG Device Channel-12 DMA Address Register" group.long 0xCB4++0x03 line.long 0x00 "OTG_DOEPDMA13,OTG Device Channel-13 DMA Address Register" group.long 0xCD4++0x03 line.long 0x00 "OTG_DOEPDMA14,OTG Device Channel-14 DMA Address Register" group.long 0xCF4++0x03 line.long 0x00 "OTG_DOEPDMA15,OTG Device Channel-15 DMA Address Register" group.long 0xB10++0x03 line.long 0x00 "OTG_DOEPTSIZ0,OTG Device OUT Endpoint 0 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" ",1 packet,2 packets,3 packets" bitfld.long 0x00 19. " PKTCNT ,Packet count bit value" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F469*")||cpuis("STM32F479*") group.long 0x930++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x950++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x970++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x990++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9B0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9D0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9F0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0xA10++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ8,OTG_HS Device Endpoint-8 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" ",1 packet,2 packets,3 packets" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif cpuis("STM32F446*") group.long 0x930++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x950++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x970++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x990++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9B0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9D0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x9F0++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0x930++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x950++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" group.long 0x970++0x03 line.long 0x00 "OTG_HS_DIEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F469*")||cpuis("STM32F479*") rgroup.long 0x918++0x03 line.long 0x00 "OTG_HS_DTXFSTS0,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x938++0x03 line.long 0x00 "OTG_HS_DTXFSTS1,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x958++0x03 line.long 0x00 "OTG_HS_DTXFSTS2,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x978++0x03 line.long 0x00 "OTG_HS_DTXFSTS3,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x998++0x03 line.long 0x00 "OTG_HS_DTXFSTS4,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9B8++0x03 line.long 0x00 "OTG_HS_DTXFSTS5,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9D8++0x03 line.long 0x00 "OTG_HS_DTXFSTS6,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9F8++0x03 line.long 0x00 "OTG_HS_DTXFSTS7,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0xA18++0x03 line.long 0x00 "OTG_HS_DTXFSTS8,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" elif cpuis("STM32F446*") rgroup.long 0x918++0x03 line.long 0x00 "OTG_HS_DTXFSTS0,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x938++0x03 line.long 0x00 "OTG_HS_DTXFSTS1,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x958++0x03 line.long 0x00 "OTG_HS_DTXFSTS2,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x978++0x03 line.long 0x00 "OTG_HS_DTXFSTS3,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x998++0x03 line.long 0x00 "OTG_HS_DTXFSTS4,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9B8++0x03 line.long 0x00 "OTG_HS_DTXFSTS5,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9D8++0x03 line.long 0x00 "OTG_HS_DTXFSTS6,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9F8++0x03 line.long 0x00 "OTG_HS_DTXFSTS7,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" else rgroup.long 0x918++0x03 line.long 0x00 "OTG_HS_DTXFSTS0,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x938++0x03 line.long 0x00 "OTG_HS_DTXFSTS1,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x958++0x03 line.long 0x00 "OTG_HS_DTXFSTS2,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x978++0x03 line.long 0x00 "OTG_HS_DTXFSTS3,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x998++0x03 line.long 0x00 "OTG_HS_DTXFSTS4,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" rgroup.long 0x9B8++0x03 line.long 0x00 "OTG_HS_DTXFSTS5,OTG_HS Device IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail" endif sif !cpuis("STM32F469*")&&!cpuis("STM32F479*") group.long 0xB10++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ0,OTG_HS Device OUT Endpoint 0 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" bitfld.long 0x00 19. " PKTCNT ,Packet count" "Low,High" hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size" endif sif cpuis("STM32F469*")||cpuis("STM32F479*") if (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x40000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x00000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x40000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x00000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x40000) group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x00000) group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x40000) group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x00000) group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xC10-0x10))&0xC0000)==0x40000) group.long 0xC10++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ8,OTG_HS Device Endpoint-8 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xC10-0x10))&0xC0000)==0x00000) group.long 0xC10++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ8,OTG_HS Device Endpoint-8 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xC10++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ8,OTG_HS Device Endpoint-8 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif elif cpuis("STM32F446*") if (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x40000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x00000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x40000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x00000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x40000) group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBD0-0x10))&0xC0000)==0x00000) group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBD0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ6,OTG_HS Device Endpoint-6 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x40000) group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBF0-0x10))&0xC0000)==0x00000) group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBF0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ7,OTG_HS Device Endpoint-7 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif else if (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x40000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB30-0x10))&0xC0000)==0x00000) group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB30++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ1,OTG_HS Device Endpoint-1 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x40000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB50-0x10))&0xC0000)==0x00000) group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB50++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ2,OTG_HS Device Endpoint-2 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x40000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB70-0x10))&0xC0000)==0x00000) group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB70++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ3,OTG_HS Device Endpoint-3 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x40000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xB90-0x10))&0xC0000)==0x00000) group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xB90++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ4,OTG_HS Device Endpoint-4 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif if (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x40000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" elif (((per.l(ad:0x40040000+0xBB0-0x10))&0xC0000)==0x00000) group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" else group.long 0xBB0++0x03 line.long 0x00 "OTG_HS_DOEPTSIZ5,OTG_HS Device Endpoint-5 Transfer Size Register" hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count" hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size" endif endif sif !cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*") rgroup.long 0x914++0x03 line.long 0x00 "OTG_HS_DIEPDMA1,Address Offset For IN Endpoint 1 Register" rgroup.long 0x934++0x03 line.long 0x00 "OTG_HS_DIEPDMA2,Address Offset For IN Endpoint 2 Register" rgroup.long 0x954++0x03 line.long 0x00 "OTG_HS_DIEPDMA3,Address Offset For IN Endpoint 3 Register" rgroup.long 0x974++0x03 line.long 0x00 "OTG_HS_DIEPDMA4,Address Offset For IN Endpoint 4 Register" rgroup.long 0x994++0x03 line.long 0x00 "OTG_HS_DIEPDMA5,Address Offset For IN Endpoint 5 Register" rgroup.long 0xB14++0x03 line.long 0x00 "OTG_HS_DOEPDMA1,Address Offset For OUT Endpoint 1 Register" rgroup.long 0xB34++0x03 line.long 0x00 "OTG_HS_DOEPDMA2,Address Offset For OUT Endpoint 2 Register" rgroup.long 0xB54++0x03 line.long 0x00 "OTG_HS_DOEPDMA3,Address Offset For OUT Endpoint 3 Register" rgroup.long 0xB74++0x03 line.long 0x00 "OTG_HS_DOEPDMA4,Address Offset For OUT Endpoint 4 Register" rgroup.long 0xB94++0x03 line.long 0x00 "OTG_HS_DOEPDMA5,Address Offset For OUT Endpoint 5 Register" endif tree.end width 16. tree "Power and clock gating control and status registers" group.long 0xE00++0x03 line.long 0x00 "OTG_HS_PCGCCTL,OTG_HS Power And Clock Gating Control Register" sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*") rbitfld.long 0x00 7. " SUSP ,Deep Sleep" "Disabled,Enabled" rbitfld.long 0x00 6. " PHYSLEEP ,PHY in Sleep" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ENL1GTG ,Enable Sleep clock gating" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended" else bitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended" endif bitfld.long 0x00 1. " GATEHCLK ,Gate HCLK" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " STPPCLK ,Stop PHY clock" "Not stopped,Stopped" tree.end width 0xB tree.end endif sif (cpuis("STM32F407*")||cpuis("STM32F417*")||cpuis("STM32F427*")||cpuis("STM32F437*")||cpuis("STM32F429*")||cpuis("STM32F439*")||cpuis("STM32F469I*")||cpuis("STM32F469B*")||cpuis("STM32F469N*")||cpuis("STM32F479I*")||cpuis("STM32F479B*")||cpuis("STM32F479N*")) tree "ETH (Ethernet)" base ad:0x40028000 width 15. tree "MAC Registers" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register" bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped" bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes" bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" textline " " bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes" bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s" bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex" textline " " bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled" bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register" bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped" bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes" bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,?..." textline " " bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes" bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s" bitfld.long 0x00 13. " ROD ,Receive own disable" "No,Yes" bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex" bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled" bitfld.long 0x00 9. " RD ,Retry disable" "No,Yes" bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes" textline " " bitfld.long 0x00 5.--6. " BL ,Back-off limit" "K = min (n.10),K = min (n.8),K = min (n.4),K = min (n.1)" bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register" sif (cpuis("STM32F2*")) bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped" textline " " endif bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes" bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes" textline " " bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s" bitfld.long 0x00 13. " ROD ,Receive own disable" "No,Yes" bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex" textline " " bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled" bitfld.long 0x00 9. " RD ,Retry disable" "No,Yes" bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes" bitfld.long 0x00 5.--6. " BL ,Back-off limit" "K = min (n.10),K = min (n.8),K = min (n.4),K = min (n.1)" textline " " bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled" bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" endif sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x40028000+0x18))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled" bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled" bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled" bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters pause frames,Forwards all,Forwards frames that pass" bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes" bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed" bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled" bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled" bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled" bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled" bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled" bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters all,Forwards all,Forwards frames that pass" bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes" bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed" bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled" bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled" bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled" endif else group.long 0x04++0x03 line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled" bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled" bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled" bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters all,Forwards all,Forwards frames that pass" bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes" bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed" bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled" bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled" bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled" endif group.long 0x08++0x0F line.long 0x00 "ETH_MACHTHR,Ethernet MAC Hash Table High Register" line.long 0x04 "ETH_MACHTLR,Ethernet MAC Hash Table Low Register" line.long 0x08 "ETH_MACMIIAR,Ethernet MAC MII Address Register" bitfld.long 0x08 11.--15. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 6.--10. " MR ,MII register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " sif (cpuis("STM32F2*")) bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-100 MHz/HCLK/42,100-120 MHz/HCLK/62,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,?..." elif (cpuis("STM32F4*")||cpuis("STM32F7*")) bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-100 MHz/HCLK/42,100-150 MHz/HCLK/62,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,150-168/HCLK/102,?..." else bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-72 MHz/HCLK/42,,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,?..." endif textline " " bitfld.long 0x08 1. " MW ,MII write" "Read,Write" eventfld.long 0x08 0. " MB ,MII busy" "Not busy,Busy" line.long 0x0C "ETH_MACMIIDR,Ethernet MAC MII Data Register" hexmask.long.word 0x0C 0.--15. 1. " MD ,MII data" if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800) group.long 0x18++0x03 line.long 0x00 "ETH_MACFCR,Ethernet MAC Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time" bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes" bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot" bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected" textline " " bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled" eventfld.long 0x00 0. " FCB ,Flow control busy" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "ETH_MACFCR,Ethernet MAC Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time" bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes" bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot" bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected" textline " " bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled" bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled" bitfld.long 0x00 0. " BPA ,Backpressure activate" "Disabled,Enabled" endif group.long 0x1C++0x03 line.long 0x00 "ETH_MACVLANTR,Ethernet MAC VLAN Tag Register" bitfld.long 0x00 16. " VLANTC ,12-bit VLAN tag comparison" "16-bits,12-bits" hexmask.long.word 0x00 0.--15. 1. " VLANTI ,VLAN tag identifier (for receive frames)" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.long 0x28++0x03 hide.long 0x00 "ETH_MACRWUFFR,Ethernet MAC Remote Wakeup Frame Filter Register" in else group.long 0x28++0x03 line.long 0x00 "ETH_MACRWUFFR,Ethernet MAC Remote Wakeup Frame Filter Register" endif hgroup.long 0x2C++0x03 hide.long 0x00 "ETH_MACPMTCSR,Ethernet MAC PMT Control And Status Register" in textline " " sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800) rgroup.long 0x34++0x03 line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register" bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty" textline " " bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated" textline " " bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO" textline " " bitfld.long 0x00 19. " MTP ,MAC transmitter in pause (full-duplex mode)" "Not paused,Paused" textline " " bitfld.long 0x00 17.--18. " TFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,Generating and transmitting a pause control frame,Transferring input frame for transmission" textline " " bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated" textline " " bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full" textline " " bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status" textline " " bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated" textline " " bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3" textline " " bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated" else rgroup.long 0x34++0x03 line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register" bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full" textline " " bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty" textline " " bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated" textline " " bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO" textline " " bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,,Transferring input frame for transmission" textline " " bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated" textline " " bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full" textline " " bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status" textline " " bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated" textline " " bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3" textline " " bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated" endif elif (cpuis("STM32F2*")) rgroup.long 0x34++0x03 line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register" bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full" bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty" textline " " bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated" bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO" textline " " bitfld.long 0x00 19. " MTP ,MAC transmitter in pause (full-duplex mode)" "Not paused,Paused" bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,Generating and transmitting a pause control frame (full duplex mode),Transferring input frame for transmission" textline " " bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated" textline " " bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full" textline " " bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status" bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated" textline " " bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3" bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated" endif textline " " sif (cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F469*")||cpuis("STM32F479*")) hgroup.word 0x38++0x01 hide.word 0x00 "ETH_MACSR,Ethernet MAC Interrupt Status Register" in else hgroup.long 0x38++0x03 hide.long 0x00 "ETH_MACSR,Ethernet MAC Interrupt Status Register" in endif sif (cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F469*")||cpuis("STM32F479*")) group.word 0x3C++0x01 line.word 0x00 "ETH_MACIMR,Ethernet MAC Interrupt Mask Register" bitfld.word 0x00 9. " TSTIM ,Time stamp trigger interrupt mask" "Not masked,Masked" bitfld.word 0x00 3. " PMTIM ,PMT interrupt mask" "Not masked,Masked" else group.long 0x3C++0x03 line.long 0x00 "ETH_MACIMR,Ethernet MAC Interrupt Mask Register" bitfld.long 0x00 9. " TSTIM ,Time stamp trigger interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " PMTIM ,PMT interrupt mask" "Not masked,Masked" endif group.long 0x40++0x1F line.long 0x00 "ETH_MACA0HR,Ethernet MAC Address 0 High Register" bitfld.long 0x00 31. " MO ,MO" "Low,High" hexmask.long.word 0x00 0.--15. 1. " MACA0H ,MAC address0 high [47:32]" line.long 0x04 "ETH_MACA0LR,Ethernet MAC Address 0 Low Register" line.long 0x08 "ETH_MACA1HR,Ethernet MAC Address 1 High Register" bitfld.long 0x08 31. " AE ,Address enable" "Disabled,Enabled" bitfld.long 0x08 30. " SA ,Source address" "DA,SA" hexmask.long.byte 0x08 24.--29. 1. " MBC ,Mask byte control" hexmask.long.word 0x08 0.--15. 1. " MACA1H ,MAC address1 high [47:32]" line.long 0x0C "ETH_MACA1LR,Ethernet MAC Address 1 Low Register" line.long 0x10 "ETH_MACA2HR,Ethernet MAC Address 2 High Register" bitfld.long 0x10 31. " AE ,Address enable" "Disabled,Enabled" bitfld.long 0x10 30. " SA ,Source address" "DA,SA" hexmask.long.byte 0x10 24.--29. 1. " MBC ,Mask byte control" hexmask.long.word 0x10 0.--15. 1. " MACA2H ,MAC address2 high [47:32]" line.long 0x14 "ETH_MACA2LR,Ethernet MAC Address 2 Low Register" line.long 0x18 "ETH_MACA3HR,Ethernet MAC Address 3 High Register" bitfld.long 0x18 31. " AE ,Address enable" "Disabled,Enabled" bitfld.long 0x18 30. " SA ,Source address" "DA,SA" hexmask.long.byte 0x18 24.--29. 1. " MBC ,Mask byte control" hexmask.long.word 0x18 0.--15. 1. " MACA3H ,MAC address2 high [47:32]" line.long 0x1C "ETH_MACA3LR,Ethernet MAC Address 3 Low Register" tree.end width 17. tree "MMC Registers" group.long 0x100++0x03 line.long 0x00 "ETH_MMCCR,Ethernet MMC Control Register" sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*")) bitfld.long 0x00 5. " MCFHP ,MMC counter full-half preset" "Not preset,Preset" bitfld.long 0x00 4. " MCP ,MMC counter preset" "Not preset,Preset" textline " " endif bitfld.long 0x00 3. " MCF ,MMC counter freeze" "Normal,Frozen" bitfld.long 0x00 2. " ROR ,Reset on read" "No reset,Reset" bitfld.long 0x00 1. " CSR ,Counter stop rollover" "Not stopped,Stopped" bitfld.long 0x00 0. " CR ,Counter reset" "No reset,Reset" sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.long 0x104++0x03 hide.long 0x00 "ETH_MMCRIR,Ethernet MMC Receive Interrupt Register" in hgroup.long 0x108++0x03 hide.long 0x00 "ETH_MMCTIR,Ethernet MMC Transmit Interrupt Register" in group.long 0x10C++0x07 line.long 0x00 "ETH_MMCRIMR,Ethernet MMC Receive Interrupt Mask Register" bitfld.long 0x00 17. " RGUFM ,Received good unicast frames mask" "Not masked,Masked" bitfld.long 0x00 6. " RFAEM ,Received frames alignment error mask" "Not masked,Masked" bitfld.long 0x00 5. " RFCEM ,Received frame CRC error mask" "Not masked,Masked" line.long 0x04 "ETH_MMCTIMR,Ethernet MMC Transmit Interrupt Mask Register" bitfld.long 0x04 21. " TGFM ,Transmitted good frames mask" "Not masked,Masked" bitfld.long 0x04 15. " TGFMSCM ,Transmitted good frames more single collision mask" "Not masked,Masked" bitfld.long 0x04 14. " TGFSCM ,Transmitted good frames single collision mask" "Not masked,Masked" endif rgroup.long 0x14C++0x07 line.long 0x00 "ETH_MMCTGFSCCR,Ethernet MMC Transmitted Good Frames After A Single Collision Counter Register" line.long 0x04 "ETH_MMCTGFMSCCR,Ethernet MMC Transmitted Good Frames After More Than A Single Collision Counter Register" rgroup.long 0x168++0x03 line.long 0x00 "ETH_MMCTGFCR,Ethernet MMC Transmitted Good Frames Counter Register" sif (cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*")) rgroup.long 0x194++0x07 line.long 0x00 "ETH_MMCRFCECR,Ethernet MMC Received Frames With CRC Error Counter Register" line.long 0x04 "ETH_MMCRFAECR,Ethernet MMC Received Frames With Alignment Error Counter Register" rgroup.long 0x1C4++0x03 line.long 0x00 "ETH_MMCRGUFCR,MMC Received Good Unicast Frames Counter Register" else hgroup.long 0x194++0x07 hide.long 0x00 "ETH_MMCRFCECR,Ethernet MMC Received Frames With CRC Error Counter Register" in hide.long 0x04 "ETH_MMCRFAECR,Ethernet MMC Received Frames With Alignment Error Counter Register" in hgroup.long 0x1C4++0x03 hide.long 0x00 "ETH_MMCRGUFCR,MMC Received Good Unicast Frames Counter Register" in endif tree.end width 14. tree "IEEE 1588 Time Stamp Registers" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x40028000+0x700))&0x30000)<=0x10000) group.long 0x700++0x03 line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register" bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer" bitfld.long 0x00 15. " TSSMRME ,Time stamp snapshot for message relevant to master enable (Ordinary/boundary clock nodes)" "Disabled,Enabled" bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled" bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled" bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled" bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled" bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled" bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated" bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated" bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized" bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated" bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled" else group.long 0x700++0x03 line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register" bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer" bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled" bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled" bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled" bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled" bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled" bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated" bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated" textline " " bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized" bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated" bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled" endif else group.long 0x700++0x03 line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register" sif (cpuis("STM32F2*")||cpuis("STM32F469*")||cpuis("STM32F479*")) bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer" bitfld.long 0x00 15. " TSSMRME ,Time stamp snapshot for message relevant to master enable (Ordinary/boundary clock nodes)" "Disabled,Enabled" bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled" bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled" bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled" bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Binary,Digital" bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated" bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated" bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled" endif group.long 0x704++0x03 line.long 0x00 "ETH_PTPSSIR,Ethernet PTP Subsecond Increment Register" hexmask.long.byte 0x00 0.--7. 1. " STSSI ,System time subsecond increment" rgroup.long 0x708++0x07 line.long 0x00 "ETH_PTPTSHR,Ethernet PTP Time Stamp High Register" line.long 0x04 "ETH_PTPTSLR,Ethernet PTP Time Stamp Low Register" bitfld.long 0x04 31. " STPNS ,System time positive or negative sign" "Positive,Negative" hexmask.long 0x04 0.--30. 1. " STSS ,System time subseconds" group.long 0x710++0x13 line.long 0x00 "ETH_PTPTSHUR,Ethernet PTP Time Stamp High Update Register" line.long 0x04 "ETH_PTPTSLUR,Ethernet PTP Time Stamp Low Update Register" bitfld.long 0x04 31. " TSUPNS ,Time stamp update positive or negative sign" "Positive,Negative" hexmask.long 0x04 0.--30. 1. " TSUSS ,Time stamp update subseconds" line.long 0x08 "ETH_PTPTSAR,Ethernet PTP Time Stamp Addend Register" line.long 0x0C "ETH_PTPTTHR,Ethernet PTP Target Time High Register" line.long 0x10 "ETH_PTPTTLR,Ethernet PTP Target Time Low Register" sif (cpuis("STM32F2*")) rgroup.long 0x728++0x03 line.long 0x00 "ETH_PTPTSSR,Ethernet PTP Time Stamp Status Register" bitfld.long 0x00 1. " TSTTR ,Time stamp target time reached" "Not reached,Reached" bitfld.long 0x00 0. " TSSO ,Time stamp second overflow" "Not overflowed,Overflowed" elif (cpuis("STM32F4*")||cpuis("STM32F7*")) hgroup.long 0x728++0x03 hide.long 0x00 "ETH_PTPTSSR,Ethernet PTP Time Stamp Status Register" in endif sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*")) rgroup.long 0x72C++0x03 line.long 0x00 "ETH_PTPPPSCR,Ethernet PTP PPS Control Register" bitfld.long 0x00 0.--3. " PPSFREQ ,PPS frequency selection" "1 Hz,2 Hz,4 Hz,8 Hz,16 Hz,32 Hz,64 Hz,128 Hz,256 Hz,512 Hz,1024 Hz,2048 Hz,4096 Hz,8192 Hz,16384 Hz,32768 Hz" endif tree.end width 15. tree "DMA Registers" sif (cpuis("STM32F4*")||cpuis("STM32F7*")) if (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800000) group.long 0x1000++0x03 line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register" bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts" bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled" bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled" bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PM ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled" bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first" bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset" elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800002) group.long 0x1000++0x03 line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register" bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts" bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled" bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled" bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled" bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled" bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first" bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset" elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x00) group.long 0x1000++0x03 line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register" bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts" bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled" bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled" bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PM ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first" bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register" bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts" bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled" bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled" bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled" bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first" bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset" endif else group.long 0x1000++0x03 line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register" sif (cpuis("STM32F2*")) bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts" textline " " endif bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled" bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled" bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled" hexmask.long.byte 0x00 17.--22. 1. " RDP ,Rx DMA PBL" textline " " bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled" bitfld.long 0x00 14.--15. " RTPR ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1" hexmask.long.byte 0x00 8.--13. 1. " PBL ,Programmable burst length" hexmask.long.byte 0x00 2.--6. 1. " DSL ,Descriptor skip length" textline " " bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first" bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset" endif group.long 0x1004++0x13 line.long 0x00 "ETH_DMATPDR,Ethernet DMA Transmit Poll Demand Register" line.long 0x04 "ETH_DMARPDR,Ethernet DMA Receive Poll Demand Register" line.long 0x08 "ETH_DMARDLAR,Ethernet DMA Receive Descriptor List Address Register" line.long 0x0C "ETH_DMATDLAR,Ethernet DMA Transmit Descriptor List Address Register" line.long 0x10 "ETH_DMASR,Ethernet DMA Status Register" rbitfld.long 0x10 29. " TSTS ,Timestamp trigger status" "No interrupt,Interrupt" rbitfld.long 0x10 28. " PMTS ,PMT status" "No interrupt,Interrupt" rbitfld.long 0x10 27. " MMCS ,MMC status" "No interrupt,Interrupt" rbitfld.long 0x10 25. " EBS[2] ,Error during data buffer/descriptor access" "Data buffer,Descriptor" textline " " rbitfld.long 0x10 24. " EBS[1] ,Error during write/read transfer" "Write,Read" rbitfld.long 0x10 23. " EBS[0] ,Error during data transfer by RxDMA/TxDMA" "RxDMA,TxDMA" rbitfld.long 0x10 20.--22. " TPS ,Transmit process state" "Stopped,Running/Fetching,Running/Waiting,Running/Reading,,,Suspended,Running/Closing" rbitfld.long 0x10 17.--19. " RPS ,Receive process state" "Stopped,Running/Fetching,,Running/Waiting,Suspended,Running/Closing,,Running/Transferring" textline " " eventfld.long 0x10 16. " NIS ,Normal interrupt summary" "Not occurred,Occurred" eventfld.long 0x10 15. " AIS ,Abnormal interrupt summary" "Not occurred,Occurred" eventfld.long 0x10 14. " ERS ,Early receive status" "No interrupt,Interrupt" eventfld.long 0x10 13. " FBES ,Fatal bus error status" "No error,Error" textline " " eventfld.long 0x10 10. " ETS ,Early transmit status" "Not tranfered,Transfered" eventfld.long 0x10 9. " RWTS ,Receive watchdog timeout status" "No timeout,Timeout" eventfld.long 0x10 8. " RPSS ,Receive process stopped status" "Not stopped,Stopped" eventfld.long 0x10 7. " RBUS ,Receive buffer unavailable status" "Available,Not available" textline " " eventfld.long 0x10 6. " RS ,Receive status" "Not completed,Completed" eventfld.long 0x10 5. " TUS ,Transmit underflow status" "No underflow,Underflow" eventfld.long 0x10 4. " ROS ,Receive overflow status" "No overflow,Overflow" eventfld.long 0x10 3. " TJTS ,Transmit jabber timeout status" "No timeout,Timeout" textline " " eventfld.long 0x10 2. " TBUS ,Transmit buffer unavailable status" "Available,Not available" eventfld.long 0x10 1. " TPSS ,Transmit process stopped status" "Not stopped,Stopped" eventfld.long 0x10 0. " TS ,Transmit status" "Not finished,Finished" if (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x00) group.long 0x1018++0x03 line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register" bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes" bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled" bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full" textline " " bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset" bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded" textline " " bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded" bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second" bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started" elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x200000) group.long 0x1018++0x03 line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register" bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes" bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled" bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full" textline " " bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset" bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded" textline " " bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded" bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second" bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started" elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x2000000) group.long 0x1018++0x03 line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register" bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes" bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled" bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full" textline " " bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset" bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded" textline " " bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded" bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second" bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started" else group.long 0x1018++0x03 line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register" bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes" bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled" bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full" textline " " bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset" bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded" textline " " bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded" bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second" bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started" endif group.long 0x101C++0x03 line.long 0x00 "ETH_DMAIER,Ethernet DMA Interrupt Enable Register" bitfld.long 0x00 16. " NISE ,Normal interrupt summary enable" "Disabled,Enabled" bitfld.long 0x00 15. " AISE ,Abnormal interrupt summary enable" "Disabled,Enabled" bitfld.long 0x00 14. " ERIE ,Early receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " FBEIE ,Fatal bus error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " ETIE ,Early transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RWTIE ,Receive watchdog timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RPSIE ,Receive process stopped interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " RBUIE ,Receive buffer unavailable interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " TUIE ,Underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ROIE ,Overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " TJTIE ,Transmit jabber timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " TBUIE ,Transmit buffer unavailable interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TPSIE ,Transmit process stopped interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled" hgroup.long 0x1020++0x03 hide.long 0x00 "ETH_DMAMFBOCR,Ethernet DMA Missed Frame And Buffer Overflow Counter Register" in group.long 0x1024++0x03 line.long 0x00 "ETH_DMARSWTR,Ethernet DMA Receive Status Watchdog Timer Register" hexmask.long.byte 0x00 0.--7. 1. " RSWTC ,Receive status (RS) watchdog timer count" rgroup.long 0x1048++0x0F line.long 0x00 "ETH_DMACHTDR,Ethernet DMA Current Host Transmit Descriptor Register" line.long 0x04 "ETH_DMACHRDR,Ethernet DMA Current Host Receive Descriptor Register" line.long 0x08 "ETH_DMACHTBAR,Ethernet DMA Current Host Transmit Buffer Address Register" line.long 0x0C "ETH_DMACHRBAR,Ethernet DMA Current Host Receive Buffer Address Register" tree.end width 0x0B tree.end endif sif (cpuis("STM32F446*")) tree "HDMI-CEC (HDMI-CEC Controller)" base ad:0x40006C00 width 10. group.long 0x00++0x03 line.long 0x00 "CEC_CR,CEC Control Register" bitfld.long 0x00 2. " TXEOM ,Tx end of message" "TXDR with EOM=0,TXDR with EOM=1" bitfld.long 0x00 1. " TXSOM ,Tx start of message" "No CEC transmission,CEC transmission" bitfld.long 0x00 0. " CECEN ,CEC enable" "Disabled,Enabled" if (((per.l((ad:0x40006C00+0x0)))&0x1)==0x0) group.long 0x04++0x03 line.long 0x00 "CEC_CFGR,CEC Configuration Register" bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge" hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address" bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically" bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated" textline " " bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated" bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated" bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped" bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended" textline " " bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods" else rgroup.long 0x04++0x03 line.long 0x00 "CEC_CFGR,CEC Configuration Register" bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge" hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address" bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically" bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated" textline " " bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated" bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated" bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped" bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended" textline " " bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods" endif wgroup.long 0x08++0x03 line.long 0x00 "CEC_TXDR,CEC Tx Data Register" hexmask.long.byte 0x00 0.--7. 1. " TXD ,Tx Data register" hgroup.long 0x0C++0x03 hide.long 0x00 "CEC_RXDR,CEC Rx Data Register" in group.long 0x10++0x03 line.long 0x00 "CEC_ISR,CEC Interrupt and Status Register" eventfld.long 0x00 12. " TXACKE ,Tx-missing acknowledge error" "No error,Error" eventfld.long 0x00 11. " TXERR ,Tx-error" "No error,Error" eventfld.long 0x00 10. " TXUDR ,Tx-buffer under-run" "Not occurred,Occurred" eventfld.long 0x00 9. " TXEND ,End of transmission" "Not occurred,Occurred" textline " " eventfld.long 0x00 8. " TXBR ,Tx-byte request" "Not occurred,Occurred" eventfld.long 0x00 7. " ARBLST ,Arbitration lost" "Not occurred,Occurred" eventfld.long 0x00 6. " RXACKE ,Rx-missing acknowledge" "No error,Error" eventfld.long 0x00 5. " LBPE ,Rx-long bit period error" "No error,Error" textline " " eventfld.long 0x00 4. " SBPE ,Rx-short bit period error" "No error,Error" eventfld.long 0x00 3. " BRE ,Rx-bit rising error" "No error,Error" eventfld.long 0x00 2. " RXOVR ,Rx-overrun" "Not occurred,Occurred" eventfld.long 0x00 1. " RXEND ,End of reception" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " RXBR ,Rx-byte received" "Not received,Received" if (((per.l(ad:0x40006C00))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "CEC_IER,CEC Interrupt Enable Register" bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled" else rgroup.long 0x14++0x03 line.long 0x00 "CEC_IER,CEC Interrupt Enable Register" bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end endif tree "DBG (Debug Registers)" base ad:0xE0042000 width 16. rgroup.long 0x00++0x03 line.long 0x00 "DBGMCU_IDCODE,MCU device ID code" sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8") hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier" bitfld.long 0x00 12.--15. " DIV_ID ,Division identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier" textline " " else hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier" hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier" endif group.long 0x04++0x0B line.long 0x00 "DBGMCU_CR,Debug MCU Configuration Register" sif (CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6"&&CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8")&&!(cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB") bitfld.long 0x00 6.--7. " TRACE_MODE ,Trace Pin Assignment Control" "Asynchronous,Synchronous/TRACEDATA=1,Synchronous/TRACEDATA=2,Synchronous/TRACEDATA=4" bitfld.long 0x00 5. " TRACE_IOEN ,Trace Pin Assignment Control" "Not assigned,Assigned" textline " " endif sif (cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||(cpuis("STM32F410*"))||(cpuis("STM32F412*"))||(cpuis("STM32F469*"))||(cpuis("STM32F479*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8") bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On" bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On" textline " " endif sif (!cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB") bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On" textline " " endif line.long 0x04 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register" sif (cpuis("STM32F2*")||cpuis("STM32F4*")) sif (!cpuis("STM32F401*"))&&!(cpuis("STM32F411*"))&&!(cpuis("STM32F410*"))&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")) bitfld.long 0x04 26. " DBG_CAN2_STOP ,Debug CAN2 stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 25. " DBG_CAN1_STOP ,Debug CAN1 stopped when Core is halted" "Started,Stopped" textline " " endif sif (cpuis("STM32F466*")||cpuis("STM32F469*")||cpuis("STM32F479*"))||(cpuis("STM32F410*")&&!cpuis("STM32F410T*"))||(cpuis("STM32F412*"))||(cpuis("STM32F479*"))||cpuis("STM32F413*")||cpuis("STM32F423?H") bitfld.long 0x04 24. " DBG_I2CFMP_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" textline " " endif sif cpuis("STM32F410*") bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" textline " " else bitfld.long 0x04 23. " DBG_I2C3_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Wachdog stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped" textline " " sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))) bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" textline " " elif cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")) bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" textline " " endif sif (!cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")) bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped" endif sif !cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")) bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped" endif elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8") sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C")) bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" textline " " bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped" bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped" textline " " bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped" textline " " sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F030CC")||cpuis("STM32F030RC") bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" textline " " endif sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F058T8")||cpuis("STM32F051T8") bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped" sif (!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")) textline " " bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped" endif else sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped" textline " " bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug Independent Watchdog stopped when Core is halted" "Started,Stopped" bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped" textline " " sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped" textline " " endif sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") bitfld.long 0x04 9. " DBG_TIM18_STOP ,TIM18 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped" textline " " sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped" textline " " endif bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped" endif line.long 0x08 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register" sif !cpuis("STM32F413*")&&!cpuis("STM32F423?H") sif (cpuis("STM32F2*")||cpuis("STM32F4*")) bitfld.long 0x08 18. " DBG_TIM11_STOP ,TIM11 counter stopped when core is halted" "Started,Stopped" sif (!cpuis("STM32F410*")) bitfld.long 0x08 17. " DBG_TIM10_STOP ,TIM10 counter stopped when core is halted" "Started,Stopped" endif textline " " bitfld.long 0x08 16. " DBG_TIM9_STOP ,TIM9 counter stopped when core is halted" "Started,Stopped" textline " " sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")) bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped" textline " " endif bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped" textline " " elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8") bitfld.long 0x08 18. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x08 17. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped" sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F051T8")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F030CC")||cpuis("STM32F030RC") textline " " bitfld.long 0x08 16. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped" endif textline " " bitfld.long 0x08 11. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped" elif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC") bitfld.long 0x08 5. " DBG_TIM19_STOP ,TIM19 counter stopped when core is halted" "Started,Stopped" textline " " endif bitfld.long 0x08 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x08 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x08 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped" textline " " sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC") bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped" textline " " endif else bitfld.long 0x08 4. " DBG_TIM11_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped" bitfld.long 0x08 3. " DBG_TIM10_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped" textline " " bitfld.long 0x08 2. " DBG_TIM9_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped" endif endif width 0x0B tree.end tree "DES (Device Electronic Signature)" base ad:0x1FFF7A10 width 7. rgroup.long 0x00++0x0B line.long 0x00 "U_ID0,Unique ID bits register 0" line.long 0x04 "U_ID1,Unique ID bits register 1" line.long 0x08 "U_ID2,Unique ID bits register 2" width 12. sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||CPUIS("STM32F301*6")||CPUIS("STM32F301*8")||CPUIS("STM32F302*6")||CPUIS("STM32F302*8")||CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||CPUIS("STM32F334*4")||CPUIS("STM32F334*6")||CPUIS("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE") rgroup.word 0x20++0x1 "Memory Size Data Register" line.word 0x00 "FLASH_SIZE,Flash size data register" elif (cpuis("STM32F4*")) rgroup.word 0x12++0x1 "Memory Size Data Register" line.word 0x00 "FLASH_SIZE,Flash size data register" endif sif (cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")||cpuis("STM32F469*")||cpuis("STM32F479*")) rgroup.word 0x1E0++0x01 "Package Data Register" line.word 0x00 "PDR,Package Data Register" sif cpuis("STM32F410*") bitfld.word 0x00 8.--10. " PKG ,Package type" "WLCSP36,UFQFPN48,,,,,,TQFP64" elif cpuis("STM32F412*") bitfld.word 0x00 8.--10. " PKG ,Package type" "UFQFPN48,LQFP64,WLCSP64,UFBGA100,LQFP100,,,UFBGA144/LQFP144" elif cpuis("STM32F413*")||cpuis("STM32F423*") bitfld.word 0x00 8.--10. " PKG ,Package type" "UFQFPN48,LQFP64,,UFBGA100/WLCSP81,LQFP100,,,UFBGA144/LQFP144" elif cpuis("STM32F469*")||cpuis("STM32F479*") bitfld.word 0x00 8.--10. " PKG ,Package type" ",WLCSP168/UFBGA169,LQFP176/UFBGA176,,LQFP208/TFBGA216,LQFP208/TFBGA216,?..." endif endif width 0x0B tree.end textline ""